LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 594

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 525. Master Transmitter mode
UM10237_4
User manual
Status
Code
(I2CSTAT)
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Status of the I
and hardware
A START condition
has been transmitted.
A repeated START
condition has been
transmitted.
SLA+W has been
transmitted; ACK has
been received.
SLA+W has been
transmitted; NOT ACK
has been received.
Data byte in I2DAT
has been transmitted;
ACK has been
received.
Data byte in I2DAT
has been transmitted;
NOT ACK has been
received.
Arbitration lost in
SLA+R/W or Data
bytes.
2
C bus
Application software response
To/From I2DAT
Load SLA+W
Clear STA
Load SLA+W or
Load SLA+R
Clear STA
Load data byte or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
Load data byte or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
Load data byte or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
Load data byte or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
Rev. 04 — 26 August 2009
To I2CON
STA STO SI
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 22: LPC24XX I
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next action taken by I
SLA+W will be transmitted; ACK bit will
be received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/REC mode.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
I
slave will be entered.
A START condition will be transmitted
when the bus becomes free.
2
C bus will be released; not addressed
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
2
C hardware
2
C block
594 of 792
2
C0/1/2