LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 596

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 527. Slave Receiver Mode
UM10237_4
User manual
Status
Code
(I2CSTAT)
0x60
0x68
0x70
0x78
0x80
0x88
0x90
Status of the I
and hardware
Own SLA+W has
been received; ACK
has been returned.
Arbitration lost in
SLA+R/W as master;
Own SLA+W has
been received, ACK
returned.
General call address
(0x00) has been
received; ACK has
been returned.
Arbitration lost in
SLA+R/W as master;
General call address
has been received,
ACK has been
returned.
Previously addressed
with own SLV
address; DATA has
been received; ACK
has been returned.
Previously addressed
with own SLA; DATA
byte has been
received; NOT ACK
has been returned.
Previously addressed
with General Call;
DATA byte has been
received; ACK has
been returned.
2
C bus
Application software response
To/From I2DAT
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
Read data byte or X
Read data byte
Read data byte or 0
Read data byte or 0
Read data byte or 1
Read data byte
Read data byte or X
Read data byte
Rev. 04 — 26 August 2009
To I2CON
STA STO SI
X
X
X
X
X
X
X
X
X
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 22: LPC24XX I
AA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next action taken by I
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomes
free.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
2
C hardware
596 of 792
2
C0/1/2