LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 613

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
5. Register description
UM10237_4
User manual
Fig 127. Simple I
TRANSMITTER
(MASTER)
2
S configurations and bus timing
SCK
WS
SD
SCK: serial clock
WS: word select
SD: serial data
Table 23–531
their functions. Following the table are details for each register.
Table 531. Summary of I
Name
I2SDAO
I2SDAI
I2STXFIFO
I2SRXFIFO
I2SSTATE
I2SDMA1
I2SDMA2
right channel
word n-1
TRANSMITTER
Description
Digital Audio Output Register. Contains control
bits for the I
Digital Audio Input Register. Contains control
bits for the I
Transmit FIFO. Access register for the 8
transmitter FIFO.
Receive FIFO. Access register for the 8
receiver FIFO.
Status Feedback Register. Contains status
information about the I
DMA Configuration Register 1. Contains control
information for DMA request 1.
DMA Configuration Register 2. Contains control
information for DMA request 2.
shows the registers associated with the I
RECEIVER
(SLAVE)
(SLAVE)
MSB
Rev. 04 — 26 August 2009
2
2
2
S registers
S transmit channel.
S receive channel.
CONTROLLER
(MASTER)
SCK
WS
SD
2
S interface.
left channel
word n
RECEIVER
TRANSMITTER
(SLAVE)
(SLAVE)
×
×
32 bit
32 bit
Chapter 23: LPC24XX I
LSB
2
S interface and a summary of
SCK: serial clock
WS: word select
SD: serial data
Access Reset
R/W
R/W
WO
RO
RO
R/W
R/W
MSB
right channel
word n+1
Value
UM10237
© NXP B.V. 2009. All rights reserved.
RECEIVER
[1]
(MASTER)
Address
0xE008 8000
0xE008 8004
0xE008 8008
0xE008 800C
0xE008 8010
0xE008 8014
0xE008 8018
2
S interface
613 of 792