LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 614

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.1 Digital Audio Output Register (I2SDAO - 0xE008 8000)
5.2 Digital Audio Input Register (I2SDAI - 0xE008 8004)
Table 531. Summary of I
[1]
The I2SDAO register controls the operation of the I
bits in DAO are shown in
Table 532: Digital Audio Output register (I2SDAO - address 0xE008 8000) bit description
The I2SDAI register controls the operation of the I
in DAI are shown in
Name
I2SIRQ
I2STXRATE
I2SRXRATE Receive bit rate divider. This register determines
Bit
1:0
2
3
4
5
14:6
15
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
wordwidth
mono
stop
reset
ws_sel
ws_halfperiod
mute
Description
Interrupt Request Control Register. Contains bits
that control how the I
generated.
Transmit bit rate divider. This register
determines the I
the value to divide pclk by in order to produce
the transmit bit clock.
the I
divide pclk by in order to produce the receive bit
clock.
2
S receive bit rate by specifying the value to
Table
Value Description
Rev. 04 — 26 August 2009
00
01
10
11
2
S registers
Table
23–533.
2
Selects the number of bytes in data as follows:
8 bit data
16 bit data
Reserved, do not use this setting
32 bit data
When one, data is of monaural format. When zero, the
data is in stereo format.
Disables accesses on FIFOs, places the transmit
channel in mute mode.
Asynchronously reset the transmit channel and FIFO.
When 0 master mode, when 1 slave mode.
Word select half period minus one, i.e. WS 64clk period
-> ws_halfperiod = 31.
When true, the transmit channel sends only zeroes.
S transmit bit rate by specifying
23–532.
2
S interrupt request is
2
S receive channel. The function of bits
2
S transmit channel. The function of
Chapter 23: LPC24XX I
Access Reset
R/W
R/W
R/W
Value
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE008 801C
0xE008 8020
0xE008 8024
2
S interface
Reset
Value
01
0
0
0
1
0x1F
1
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