LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 617

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
6. I
UM10237_4
User manual
2
S transmit and receive interfaces
5.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)
5.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)
Table 539: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description
The bit rate for the I
The value depends on the audio sample rate desired, and the data size and format
(stereo/mono) used. For example, a 48 kHz sample rate for 16 bit stereo data requires a
bit rate of 48,000×16×2 = 1.536 MHz.
Table 540: Transmit Clock Rate register (I2TXRATE - address 0xE008 8020) bit description
The bit rate for the I
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2STXRATE.
Table 541: Receive Clock Rate register (I2SRXRATE - address 0xE008 8024) bit description
The I
information. Some details of I
Bit
0
1
7:2
15:8
23:16
31:24
Bit
9:0
15:10
Bit
9:0
15:10
•
•
•
When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
When mute is true, the data value 0 is transmitted.
When mono is false, two successive data words are respectively left and right data.
2
S interface can transmit and receive 8, 16 or 32 bits stereo or mono audio
Symbol
rx_Irq_enable
tx_Irq_enable
Unused
rx_depth_Irq
tx_depth_Irq
-
Symbol
tx_rate
Unused
Symbol
rx_rate
Unused
Description
I
to produce the transmit bit clock. Ten bits of divide supports a wide
range of I
Unused.
Description
I
to produce the receive bit clock. Ten bits of divide supports a wide
range of I
Unused.
2
2
2
2
S transmitter is determined by the value of the I2STXRATE register.
S receiver is determined by the value of the I2SRXRATE register.
S transmit bit rate. This value plus one is used to divide PCLK by
S receive bit rate. This value plus one is used to divide PCLK by
Rev. 04 — 26 August 2009
2
2
Description
When 1, enables I2S receive interrupt.
When 1, enables I2S transmit interrupt.
Unused.
Set the FIFO level on which to create an irq request.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Set the FIFO level on which to create an irq request.
S rates over a wide range of pclk rates.
S rates over a wide range of pclk rates.
2
S implementation are:
Chapter 23: LPC24XX I
UM10237
© NXP B.V. 2009. All rights reserved.
2
S interface
Reset
Value
0
0
0
0
0
NA
Reset
Value
0
0
Reset
Value
0
0
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