LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 628

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
6.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028,
6.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
0xE007 0028, 0xE007 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 551: Capture Control Register (T[0/1/2/3]CCR - addresses 0xE000 4028, 0xE000 8020,
Bit
0
1
2
3
4
5
15:6
Symbol
CAP0RE 1
CAP0FE 1
CAP0I
CAP1RE 1
CAP1FE 1
CAP1I
-
0xE007 0028, 0xE007 4028) bit description
Value Description
0
0
1
0
0
0
1
0
Rev. 04 — 26 August 2009
Capture on CAPn.0 rising edge: a sequence of 0 then 1 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event
will generate an interrupt.
This feature is disabled.
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event
will generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
628 of 792
Reset
Value
0
0
0
0
0
0
NA