LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 635

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.1 Rules for single edge controlled PWM outputs
3.2 Rules for double edge controlled PWM outputs
3.3 Summary of differences from the standard timer block
Five rules are used to determine the next value of a PWM output when a new cycle is
about to begin:
1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle
2. Each PWM output will go low when its match value is reached. If no match occurs (i.e.
1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time
2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0
3. When match values are changing, if one of the "old" match values is equal to the
4. If both a set and a clear of a PWM output are requested at the same time, clear takes
5. If a match value is out of range (i.e. greater than the PWM rate value), no match event
1. A synchronizing register (shadow register) is added to each match register to allow
2. A new Load Enable Register (LER) is added to allow software to control Match
3. A single PWM mode bit is added to the TCR register. The PWM mode enables
4. A Master Enable bit is added to the TCR register, the value of which is brought out of
unless their match value is equal to 0.
the match value is greater than the PWM rate), the PWM output remains continuously
high.
point which is coincident with the beginning of the next PWM cycle), except as noted
in rule 3.
value) have the same effect, except as noted in rule 3. For example, a request for a
falling edge at the beginning of the PWM cycle has the same effect as a request for a
falling edge at the end of a PWM cycle.
PWM rate, it is used again once if the neither of the new match values are equal to 0
or the PWM rate, and there was no old match value equal to 0.
precedence. This can occur when the set and clear match values are the same as in,
or when the set or clear value equals 0 and the other value equals the PWM rate.
occurs and that match channel has no effect on the output. This means that the PWM
output will remain always in one state, allowing always low, always high, or
"no change" outputs.
changes to take effect only when requested by software, and only at the transition
between PWM cycles.
register updates. The LER contains one bit for each Match register. When a bit in the
LER is written with a one, the shadow register contents for the corresponding Match
channel are loaded into the actual Match register when the counter is reset (when
Match 0 occurs). LER bits are reset automatically when the counter is reset.
loading the actual match registers from the shadow registers under
software/hardware control as described above. When PWM mode is not enabled, the
match value shadow registers are either transparent or bypassed.
the PWM block. An external enable input is added to the PWM block, that is
connected to the Master Enable output of the Master PWM block.
Rev. 04 — 26 August 2009
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
UM10237
© NXP B.V. 2009. All rights reserved.
635 of 792