LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 640

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 559: PWM Timer Control Register (PWM0TCR - address 0xE001 4004 PWM1TCR address 0xE001 8004) bit
UM10237_4
User manual
Bit
0
1
2
3
4
7:5
Symbol
Counter Enable 1
Counter Reset
-
PWM Enable
Master Disable
(PWM0 only)
-
description
6.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and
Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address
PWM1TCR 0xE001 8004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in
Bit
9
10
15:11 -
Value
0
1
0
1
0
1
0
Symbol
PWMMR5 Interrupt Interrupt flag for PWM match channel 5.
PWMMR6 Interrupt Interrupt flag for PWM match channel 6.
0xE001 8000) bit description
Description
The PWM Timer Counter and PWM Prescale Counter are
enabled for counting.
The counters are disabled.
The PWM Timer Counter and the PWM Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until this bit is returned to zero.
Clear reset.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
PWM mode is enabled (counter resets to 1). PWM mode
causes the shadow registers to operate in connection with
the Match registers. A program write to a Match register will
not have an effect on the Match result until the
corresponding bit in PWMLER has been set, followed by the
occurrence of a PWM Match 0 event. Note that the PWM
Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being
enabled. Otherwise a Match event will not occur to cause
shadow register contents to become effective.
Timer mode is enabled (counter resets to 0).
The two PWMs may be synchronized using the Master
Disable control bit. The Master disable bit of the Master
PWM (PWM0 module) controls a secondary enable input to
both PWMs, as shown in
This bit has no function in the Slave PWM (PWM1).
PWM0 is the master, and both PWMs are enabled for
counting.
The PWM’s are used independently, and the individual
Counter Enable bits are used to control the PWM’s.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Figure
25–132.
Table
25–559.
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
NA
0
0
NA
640 of 792
Reset
Value
0
0
NA