LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 672

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)
5.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 596: A/D Interrupt Enable Register (AD0INTEN - address 0xE003 400C) bit description
0xE003 402C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 597: A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0xE003 4010 to
Bit
7:0
8
31:9 Unused
Bit
5:0
15:6
29:16 Unused
30
31
Symbol
ADINTEN 7:0 These bits allow control over which A/D channels generate
ADGINTEN
Symbol
Unused
V/V
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
DONE
REF
0xE003 402C) bit description
Description
Unused, always 0.
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
When DONE is 1, this field contains a binary fraction representing the
voltage on the Ain pin, divided by the voltage on the Vref pin. Zero in
the field indicates that the voltage on the Ain pin was less than, equal
to, or close to that on V
Ain was close to, equal to, or greater than that on Vref.
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
was (were) lost and overwritten before the conversion that produced
the result in the LS bits.This bit is cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
Description
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Unused, always 0.
Rev. 04 — 26 August 2009
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
REF
, while 0x3FF indicates that the voltage on
UM10237
© NXP B.V. 2009. All rights reserved.
672 of 792
Reset
Value
0x00
1
0
Reset
Value
0
NA
0
0
0