LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 71

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.2.1 Memory transaction endianness
5.2.2 Memory transaction size
5.2.3 Write protected memory areas
5.4.1 Write buffers
5.2 AHB slave memory interface
5.3 Pad interface
5.4 Data buffers
The AHB slave memory interface allows access to external memories.
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the EMCConfig register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.
The pad interface block provides the interface to the pads. The pad interface uses
feedback clocks, FBCLKIN[3:0], to resynchronize SDRAM read data from the off-chip to
on-chip domains.
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also
be disabled when performing SyncFlash commands. The buffers must be enabled during
normal operation.
The buffers can be enabled or disabled for static memory using the EMCStaticConfig
Registers.
Write buffers are used to:
Write buffer operation:
•
•
Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.
Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Rev. 04 — 26 August 2009
Chapter 5: LPC24XX External Memory Controller (EMC)
UM10237
© NXP B.V. 2009. All rights reserved.
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