LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 719

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.3 Enabling a DMA channel
5.4 Disabling a DMA channel
5.5 Disabling a DMA channel without losing data in the FIFO
5.6 Setup a new DMA transfer
5.7 Disabling a DMA channel and losing data in the FIFO
5.8 Halting a DMA transfer
To enable the DMA channel set the Channel Enable bit in the relevant DMA channel
Configuration Register (
(DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0
Note: The channel must be fully initialized before it is enabled. Additionally, you must set
the Enable bit of the GPDMA before any channels are enabled.
You can disable a DMA channel in the following ways:
To disable a DMA channel without losing data in the FIFO:
To set up a new DMA transfer:
Clear the relevant Channel Enable bit in the relevant channel Configuration Register
(Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration -
0xFFE0 4110 and DMACC1Configuration - 0xFFE0
one is in progress, completes and the channel is disabled. Any data in the FIFO is lost.
Set the Halt bit in the relevant DMA channel Configuration Register. The current source
request is serviced. Any further source DMA requests are ignored until the Halt bit is
cleared.
1. Set the Halt bit in the relevant channel Configuration Register
2. Poll the Active bit in the relevant channel Configuration Register until it reaches 0.
3. Clear the Channel Enable bit in the relevant channel Configuration Register.
1. If the channel is not set aside for the DMA transaction:
2. Program the GPDMA.
•
•
•
Write directly to the Channel Enable bit. Any outstanding data in the FIFOs is lost if
this method is used.
Use the Active and Halt bits in conjunction with the Channel Enable bit.
Wait until the transfer completes. The channel is then automatically disabled.
“Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0
be ignored.
This bit indicates whether there is any data in the channel which has to be transferred.
– Read the DMACEnbldChns Register and find out which channels are inactive (see
– Choose an inactive channel that has the required priority.
Section 32–6.1.8 “Enabled Channel Register (DMACEnbldChns - 0xFFE0
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Section 32–6.2.6 “Channel Configuration Registers
4130)”). This causes any further DMA requests to
4130)”). The current AHB transfer, if
(Section 32–6.2.6
UM10237
© NXP B.V. 2009. All rights reserved.
4130)”).
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401C)”).