LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 726

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
6.1.13 Configuration Register (DMACConfiguration - 0xFFE0 4030)
6.1.14 Synchronization Register (DMACSync - 0xFFE0 4034)
Table 664. Software Last Single Request register (DMACSoftLSReq - address 0xFFE0 402C)
The DMACConfiguration Register is read/write and configures the operation of the
GPDMA. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
Table 32–665
Table 665. Configuration register (DMACConfiguration - address 0xFFE0 4030) bit
The DMACSync Register is read/write and enables or disables synchronization logic for
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the
synchronization logic for a particular group of DMA requests. This register is reset to 0,
synchronization logic enabled.
Table 32–666
Table 666. Synchronization register (DMACSync - address 0xFFE0 4034) bit description
Bit
3:0
4
31:5
Bit
0
1
31:2
Bit
15:0
31:16 -
Symbol Value Description
E
M
-
Symbol
DMACSync
Symbol
-
SoftLSReqSDMMC
-
bit description
description
shows the bit assignments of the DMACConfiguration Register.
shows the bit assignments of the DMACSync Register.
0
1
0
1
-
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Description
DMA synchronization logic for DMA request signals enabled or
disabled. A LOW bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0],
DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals
is enabled. A HIGH bit indicates that the synchronization logic
is disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
GPDMA enable:
Disabled. Disabling the GPDMA reduces power consumption.
Enabled.
AHB Master endianness configuration:
Little-endian mode.
Big-endian mode.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Software last single request flags for SD/MMC.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0x0000
NA
Reset
Value
0
0
NA
Reset
Value
NA
0
NA