LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 735
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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Manufacturer
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Price
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LPC2468FET208,551
Manufacturer:
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Quantity:
6 174
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LPC2468FET208,551
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9. Interrupt requests
UM10237_4
User manual
The second LLI, stored at 0x20010 , describes the next block of data to be transferred:
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x20000, is programmed into the GPDMA. When the first
packet of data has been transferred the next LLI is automatically loaded.
The final LLI is stored at 0x20070 and contains:
Because the next LLI address is set to zero, this is the last descriptor, and the DMA
channel is disabled after transferring the last item of data. The channel is probably set to
generate an interrupt at this point to indicate to the ARM processor that the channel can
be reprogrammed.
Interrupt requests can be generated when an AHB error is encountered, or at the end of a
transfer (terminal count) after all the data corresponding to the current LLI has been
transferred to the destination. The interrupts can be masked by programming bits in the
relevant DMACCxControl and DMACCxConfiguration Channel Registers. Interrupt status
registers are provided which group the interrupt requests from all the DMA channels prior
to interrupt masking (DMACRawIntTCStatus and DMACRawIntErrorStatus), and after
interrupt masking (DMACIntTCStatus and DMACIntErrorStatus). The DMACIntStatus
Register combines both the DMACIntTCStatus and DMACIntErrorStatus requests into a
single register to enable the source of an interrupt to be quickly found. Writing to the
DMACIntTCClear or the DMACIntErrClr Registers with a bit set HIGH enables selective
clearing of interrupts.
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Source start address 0x0A200.
Destination address set to the destination peripheral address.
Transfer width, word (32 bit).
Transfer size, 3 072 bytes (0XC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x20010.
Source start address 0x0B200.
Destination address set to the destination peripheral address.
Transfer width, word (32 bit).
Transfer size, 3 072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x20020.
Source start address 0x11200.
Destination address set to the destination peripheral address.
Transfer width, word (32 bit).
Transfer size, 3 072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x0.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
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