LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 765

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 229.Interrupt Enable register (intEnable - address
Table 230.Interrupt Clear register (IntClear - address
Table 231.Interrupt Set register (IntSet - address
Table 232.Power-Down register (PowerDown - address
Table 233.Receive Descriptor Fields. . . . . . . . . . . . . . . .243
Table 234.Receive Descriptor Control Word . . . . . . . . . .243
Table 235.Receive Status Fields . . . . . . . . . . . . . . . . . . .243
Table 236.Receive Status HashCRC Word . . . . . . . . . . .243
Table 237.Receive status information word. . . . . . . . . . .244
Table 238.Transmit descriptor fields . . . . . . . . . . . . . . . .246
Table 239.Transmit descriptor control word . . . . . . . . . .246
Table 240.Transmit status fields . . . . . . . . . . . . . . . . . . .246
Table 241.Transmit status information word . . . . . . . . . .247
Table 242.LCD controller pins . . . . . . . . . . . . . . . . . . . . .284
Table 243.Pins used for single panel STN displays . . . .284
Table 244.Pins used for dual panel STN displays . . . . . .285
Table 245.Pins used for TFT displays . . . . . . . . . . . . . . .285
Table 246.FIFO bits for Little-endian Byte, Little-endian Pixel
Table 247.FIFO bits for Big-endian Byte, Big-endian Pixel
Table 248.FIFO bits for Little-endian Byte, Big-endian Pixel
Table 249.RGB mode data formats . . . . . . . . . . . . . . . . .292
Table 250.Palette data storage for TFT modes. . . . . . . .293
Table 251.Palette data storage for STN color modes.. . .293
Table 252.Palette data storage for STN monochrome
Table 253.Palette data storage for STN monochrome
Table 254.Addresses for 32 x 32 cursors . . . . . . . . . . . .297
Table 255.Buffer to pixel mapping for 32 x 32 pixel cursor
Table 256.Buffer to pixel mapping for 64 x 64 pixel cursor
Table 257.Pixel encoding . . . . . . . . . . . . . . . . . . . . . . . .299
Table 258.Color display driven with 2 2/3 pixel data . . . .300
Table 259.Summary of LCD controller registers . . . . . . .303
Table 260.LCD Configuration register (LCD_CFG, RW -
Table 261.Horizontal Timing register (LCD_TIMH, RW -
Table 262.Vertical Timing register (LCD_TIMV, RW - 0xFFE1
Table 263.Clock and Signal Polarity register (LCD_POL, RW
Table 264.Line End Control register (LCD_LE, RW - 0xFFE1
Table 265.Upper Panel Frame Base register
Table 266.Lower Panel Frame Base register
Table 267.LCD Control register (LCD_CTRL, RW - 0xFFE1
UM10237_4
User manual
0xFFE0 0FE0) bit description . . . . . . . . . . . . .239
0xFFE0 0FE4) bit description . . . . . . . . . . . . .239
0xFFE0 0FE8) bit description . . . . . . . . . . . . .240
0xFFE0 0FEC) bit description. . . . . . . . . . . . .241
0xFFE0 0FF4) bit description . . . . . . . . . . . . .241
order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
0xE01F C1B8) . . . . . . . . . . . . . . . . . . . . . . . .304
0xFFE1 0000) . . . . . . . . . . . . . . . . . . . . . . . . .305
0004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
- 0xFFE1 0008). . . . . . . . . . . . . . . . . . . . . . . .307
000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
(LCD_UPBASE, RW - 0xFFE1 0010). . . . . . .310
(LCD_LPBASE, RW - 0xFFE1 0014) . . . . . . . 311
Rev. 04 — 26 August 2009
Table 268.Interrupt Mask register (LCD_INTMSK, RW -
Table 269.Raw Interrupt Status register (LCD_INTRAW, RW
Table 270.Masked Interrupt Status register (LCD_INTSTAT,
Table 271.Interrupt Clear register (LCD_INTCLR, RW -
Table 272.Upper Panel Current Address register
Table 273.Lower Panel Current Address register
Table 274.Color Palette registers (LCD_PAL, RW - 0xFFE1
Table 275.Cursor Image registers (CRSR_IMG, RW -
Table 276.Cursor Control register (CRSR_CTRL, RW -
Table 277.Cursor Configuration register (CRSR_CFG, RW -
Table 278.Cursor Palette register 0 (CRSR_PAL0, RW -
Table 279.Cursor Palette register 1 (CRSR_PAL1, RW -
Table 280.Cursor XY Position register (CRSR_XY, RW -
Table 281.Cursor Clip Position register (CRSR_CLIP, RW -
Table 282.Cursor Interrupt Mask register (CRSR_INTMSK,
Table 283.Cursor Interrupt Clear register (CRSR_INTCLR,
Table 284.Cursor Raw Interrupt Status register
Table 285.Cursor Masked Interrupt Status register
Table 286.LCD panel connections for STN single panel
Table 287.LCD panel connections for STN dual panel mode
Table 288.LCD panel connections for TFT panels . . . . . 327
Table 289.USB related acronyms, abbreviations, and
Table 290.Fixed endpoint configuration . . . . . . . . . . . . . 330
Table 291.USB device pin description . . . . . . . . . . . . . . 334
Table 292.USB device controller clock sources . . . . . . . 335
Table 293.Summary of USB device registers . . . . . . . . 336
Table 294.USB Port Select register (USBPortSel - address
Table 295.USBClkCtrl register (USBClkCtrl - address
Table 296.USB Clock Status register (USBClkSt - 0xFFE0
Table 297.USB Interrupt Status register (USBIntSt - address
Table 298.USB Device Interrupt Status register
Chapter 36: LPC24XX Supplementary information
0018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
0xFFE1 001C) . . . . . . . . . . . . . . . . . . . . . . . . 313
- 0xFFE1 0020) . . . . . . . . . . . . . . . . . . . . . . . 314
RW - 0xFFE1 0024) . . . . . . . . . . . . . . . . . . . . 315
0xFFE1 0028) . . . . . . . . . . . . . . . . . . . . . . . . 315
(LCD_UPCURR, RW - 0xFFE1 002C). . . . . . 316
(LCD_LPCURR, RW - 0xFFE1 0030) . . . . . . 316
0200 to 0xFFE1 03FC) . . . . . . . . . . . . . . . . . 317
0xFFE1 0800 to 0xFFE1 0BFC) . . . . . . . . . . 318
0xFFE1 0C00) . . . . . . . . . . . . . . . . . . . . . . . . 318
0xFFE1 0C04) . . . . . . . . . . . . . . . . . . . . . . . . 319
0xFFE1 0C08) . . . . . . . . . . . . . . . . . . . . . . . . 319
0xFFE1 0C0C) . . . . . . . . . . . . . . . . . . . . . . . . 320
0xFFE1 0C10) . . . . . . . . . . . . . . . . . . . . . . . . 320
0xFFE1 0C14) . . . . . . . . . . . . . . . . . . . . . . . . 321
RW - 0xFFE1 0C20). . . . . . . . . . . . . . . . . . . . 321
RW - 0xFFE1 0C24). . . . . . . . . . . . . . . . . . . . 321
(CRSR_INTRAW, RW - 0xFFE1 0C28) . . . . . 322
(CRSR_INTSTAT, RW - 0xFFE1 0C2C) . . . . 322
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
326
definitions used in this chapter. . . . . . . . . . . . 329
0xFFE0 C110) bit description. . . . . . . . . . . . . 338
0xFFE0 CFF4) bit description . . . . . . . . . . . . 338
CFF8) bit description . . . . . . . . . . . . . . . . . . . 339
0xE01F C1C0) bit description . . . . . . . . . . . . 339
(USBDevIntSt - address 0xFFE0 C200) bit
UM10237
© NXP B.V. 2009. All rights reserved.
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