LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 767

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 345.USB System Error Interrupt Clear register
Table 346.USB System Error Interrupt Set register
Table 347.SIE command code table . . . . . . . . . . . . . . . .364
Table 348.Device Set Address Register bit description. .364
Table 349.Configure Device Register bit description. . . .365
Table 350.Set Mode Register bit description. . . . . . . . . .365
Table 351.Set Device Status Register bit description . . .366
Table 352.Get Error Code Register bit description . . . . .368
Table 353.Read Error Status Register bit description . . .368
Table 354.Select Endpoint Register bit description . . . . .369
Table 355.Set Endpoint Status Register bit description. .370
Table 356.Clear Buffer Register bit description . . . . . . . .371
Table 357.DMA descriptor . . . . . . . . . . . . . . . . . . . . . . . .376
Table 358.USB (OHCI) related acronyms and abbreviations
Table 359.USB OTG port pins. . . . . . . . . . . . . . . . . . . . .390
Table 360.USB Host register address definitions . . . . . .392
Table 361.USB OTG port 1 pins . . . . . . . . . . . . . . . . . . .396
Table 362.USB OTG and I2C register address
Table 363.USB Interrupt Status register - (USBIntSt -
Table 364.OTG Interrupt Status register (OTGIntSt - address
Table 365.OTG Status Control register (OTGStCtrl - address
Table 366.Port function truth table. . . . . . . . . . . . . . . . . .404
Table 367.OTG Timer register (OTGTmr - address
Table 368.OTG_clock_control register (OTG_clock_control -
Table 369.OTG_clock_status register (OTGClkSt - address
Table 370.I2C Receive register (I2C_RX - address
Table 371.I2C Transmit register (I2C_TX - address
Table 372.I2C status register (I2C_STS - address
Table 373.I2C Control register (I2C_CTL - address
Table 374.I2C_CLKHI register (I2C_CLKHI - address
Table 375.I2C_CLKLO register (I2C_CLKLO - address
Table 376.UART0 Pin description . . . . . . . . . . . . . . . . . .423
Table 377.UART Register Map . . . . . . . . . . . . . . . . . . . .425
Table 378.UARTn Receiver Buffer Register (U0RBR -
Table 379.UART0 Transmit Holding Register (U0THR -
UM10237_4
User manual
(USBSysErrIntClr - address 0xFFE0 C2BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .360
(USBSysErrIntSet - address 0xFFE0 C2C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .360
used in this chapter . . . . . . . . . . . . . . . . . . . .389
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
address 0xE01F C1) bit description . . . . . . . .401
0xE01F C100) bit description . . . . . . . . . . . . .402
0xFFE0 C110) bit description . . . . . . . . . . . . .403
0xFFE0 C114) bit description . . . . . . . . . . . . .404
address 0xFFE0 CFF4) bit description . . . . . .404
0xFFE0 CFF8) bit description. . . . . . . . . . . . .405
0xFFE0 C300) bit description . . . . . . . . . . . . .406
0xFFE0 C300) bit description . . . . . . . . . . . . .406
0xFFE0 C304) bit description . . . . . . . . . . . . .407
0xFFE0 C308) bit description . . . . . . . . . . . . .408
0xFFE0 C30C) bit description. . . . . . . . . . . . .409
0xFFE0 C310) bit description . . . . . . . . . . . . .410
address 0xE000 C000, U2RBR - 0xE007 8000,
U3RBR - 0E007 C000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . .427
address 0xE000 C000, U2THR - 0xE007 8000,
U3THR - 0xE007 C000 when DLAB = 0, Write
Rev. 04 — 26 August 2009
Table 380.UARTn Divisor Latch LSB Register (U0DLL -
Table 381.UARTn Divisor Latch MSB Register (U0DLM -
Table 382.UARTn Interrupt Enable Register (U0IER -
Table 383.UARTn Interrupt Identification Register (U0IIR -
Table 384.UARTn Interrupt Handling . . . . . . . . . . . . . . . 430
Table 385.UARTn FIFO Control Register (U0FCR - address
Table 386.UARTn Line Control Register (U0LCR - address
Table 387.UARTn Line Status Register (U0LSR - address
Table 388.UARTn Scratch Pad Register (U0SCR - address
Table 389.UARTn Auto-baud Control Register (U0ACR -
Table 390.IrDA Control Register for UART3 only (U3ICR -
Table 391.IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 437
Table 392.UARTn Fractional Divider Register (U0FDR -
Table 393.Fractional Divider setting look-up table . . . . . 440
Table 394.UARTn Transmit Enable Register (U0TER -
Table 395:UART1 Pin Description . . . . . . . . . . . . . . . . . 444
Table 396.UART1 register map . . . . . . . . . . . . . . . . . . . 445
Table 397.UART1 Receiver Buffer Register (U1RBR -
Table 398.UART1 Transmitter Holding Register (U1THR -
Table 399.UART1 Divisor Latch LSB Register (U1DLL -
Table 400.UART1 Divisor Latch MSB Register (U1DLM -
Table 401.UART1 Interrupt Enable Register (U1IER -
Chapter 36: LPC24XX Supplementary information
Only) bit description . . . . . . . . . . . . . . . . . . . . 427
address 0xE000 C000, U2DLL - 0xE007 8000,
U3DLL - 0xE007 C000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
address 0xE000 C004, U2DLM - 0xE007 8004,
U3DLM - 0xE007 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
address 0xE000 C004, U2IER - 0xE007 8004,
U3IER - 0xE007 C004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
address 0xE000 C008, U2IIR - 0x7008 8008,
U3IIR - 0x7008 C008, Read Only)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 429
0xE000 C008, U2FCR - 0xE007 8008, U3FCR -
0xE007 C008, Write Only) bit description . . . 431
0xE000 C00C, U2LCR - 0xE007 800C, U3LCR -
0xE007 C00C) bit description . . . . . . . . . . . . 432
0xE000 C014, U2LSR - 0xE007 8014, U3LSR -
0xE007 C014, Read Only) bit description . . . 432
0xE000 C01C, U2SCR - 0xE007 801C, U3SCR -
0xE007 C01C) bit description . . . . . . . . . . . . 434
0xE000 C020, U2ACR - 0xE007 8020, U3ACR -
0xE007 C020) bit description. . . . . . . . . . . . . 434
address 0xE007 C024) bit description . . . . . . 437
address 0xE000 C028, U2FDR - 0xE007 8028,
U3FDR - 0xE007 C028) bit description . . . . . 438
address 0xE000 C030, U2TER - 0xE007 8030,
U3TER - 0xE007 C030) bit description . . . . . 441
address 0xE001 0000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 447
address 0xE001 0000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 447
address 0xE001 0000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
address 0xE001 0004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
UM10237
© NXP B.V. 2009. All rights reserved.
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