LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 773

IC ARM7 MCU FLASH 512K 208TFBGA

LPC2468FET208,551

Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2468FET208,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Part Number:
LPC2468FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
4. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Reset block diagram including the wakeup timer.32
Fig 11. Example of start-up after reset. . . . . . . . . . . . . . .33
Fig 12. Clock generation for the LPC2400. . . . . . . . . . . .42
Fig 13. Oscillator modes and models: a) slave mode of
Fig 14. PLL block diagram (N = 16, M = 125, USBSEL = 6,
Fig 15. EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .70
Fig 16. 32 bit bank external memory interfaces ( bits
Fig 17. 16 bit bank external memory interfaces (bits
Fig 18. 8 bit bank external memory interface
Fig 19. Typical memory configuration diagram . . . . . . .100
Fig 20. Simplified block diagram of the Memory Accelerator
Fig 21. Block diagram of the Memory Accelerator
Fig 22. Block diagram of the Vectored Interrupt
Fig 23. LPC2458 pinning TFBGA180 package . . . . . . .120
Fig 24. LPC2400 pinning LQFP208 package . . . . . . . .121
Fig 25. LPC2400 pinning TFBGA208 package . . . . . . .121
Fig 26. Ethernet block diagram . . . . . . . . . . . . . . . . . . .213
Fig 27. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .217
Fig 28. Receive descriptor memory layout. . . . . . . . . . .242
Fig 29. Transmit descriptor memory layout . . . . . . . . . .245
Fig 30. Transmit example memory and registers. . . . . .256
Fig 31. Receive Example Memory and Registers . . . . .262
Fig 32. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .267
Fig 33. Receive filter block diagram. . . . . . . . . . . . . . . .269
Fig 34. Receive Active/Inactive state machine . . . . . . .273
Fig 35. Transmit Active/Inactive state machine . . . . . . .274
Fig 36. LCD controller block diagram. . . . . . . . . . . . . . .287
Fig 37. Cursor movement . . . . . . . . . . . . . . . . . . . . . . .295
Fig 38. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .296
Fig 39. Cursor image format . . . . . . . . . . . . . . . . . . . . .297
Fig 40. Power-up and power-down sequences . . . . . . .303
Fig 41. Horizontal timing for STN displays. . . . . . . . . . .323
Fig 42. Vertical timing for STN displays . . . . . . . . . . . . .324
Fig 43. Horizontol timing for TFT displays . . . . . . . . . . .324
Fig 44. Vertical timing for TFT displays . . . . . . . . . . . . .325
Fig 45. USB device controller block diagram . . . . . . . . .332
Fig 46. USB MaxPacketSize register array indexing . . .350
UM10237_4
User manual
LPC2458 block diagram . . . . . . . . . . . . . . . . . . . 11
LPC2460 block diagram . . . . . . . . . . . . . . . . . . .12
LPC2468 block diagram . . . . . . . . . . . . . . . . . . .13
LPC2470 block diagram . . . . . . . . . . . . . . . . . . .14
LPC2478 block diagram . . . . . . . . . . . . . . . . . . .15
LPC2400 system memory map . . . . . . . . . . . . . .18
Peripheral memory map. . . . . . . . . . . . . . . . . . . .19
AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .20
Map of lower memory is showing re-mapped and
re-mappable areas for a LPC2400 part with flash25
operation, b) oscillation mode of operation, c)
external crystal model used for C
CCLKSEL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . .47
MW = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
MW = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
(bits MW = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
X1
/
X2
evaluation44
Rev. 04 — 26 August 2009
Fig 47. Interrupt event handling . . . . . . . . . . . . . . . . . . 362
Fig 48. UDCA Head register and DMA Descriptors . . . 375
Fig 49. Isochronous OUT endpoint operation example. 383
Fig 50. Data transfer in ATLE mode . . . . . . . . . . . . . . . 384
Fig 51. USB Host controller block diagram . . . . . . . . . . 390
Fig 52. USB OTG controller block diagram. . . . . . . . . . 395
Fig 53. USB OTG port configuration: port U1 OTG
Fig 54. USB OTG port configuration: VP_VM mode . . . 398
Fig 55. USB OTG port configuration: port U2 host, port U1
Fig 56. USB OTG port configuration: port U1 host, port U2
Fig 57. Port selection for PORT_FUNC bit 0 = 0 and
Fig 58. USB OTG interrupt handling . . . . . . . . . . . . . . . 410
Fig 59. USB OTG controller with software stack . . . . . . 412
Fig 60. Hardware support for B-device switching from
Fig 61. State transitions implemented in software during
Fig 62. Hardware support for A-device switching from host
Fig 63. State transitions implemented in software during
Fig 64. Clocking and power control. . . . . . . . . . . . . . . . 420
Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 436
Fig 66. Algorithm for setting UART dividers . . . . . . . . . 439
Fig 67. UART0, 2 and 3 block diagram . . . . . . . . . . . . . 442
Fig 68. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 454
Fig 69. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 455
Fig 70. Auto-baud a) mode 0 and b) mode 1 waveform 461
Fig 71. Algorithm for setting UART dividers . . . . . . . . . 463
Fig 72. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 466
Fig 73. CAN controller block diagram . . . . . . . . . . . . . . 469
Fig 74. Transmit buffer layout for standard and extended
Fig 75. Receive buffer layout for standard and extended
Fig 76. Global Self-Test (high-speed CAN Bus
Fig 77. Local self test (high-speed CAN Bus example). 472
Fig 78. Entry in FullCAN and individual standard identifier
Fig 79. Entry in standard identifier range table . . . . . . . 499
Fig 80. Entry in either extended identifier table . . . . . . . 499
Fig 81. ID Look-up table example explaining the search
Fig 82. Semaphore procedure for reading an auto-stored
Fig 83. FullCAN section example of the ID
Fig 84. FullCAN message object layout . . . . . . . . . . . . 512
Fig 85. Normal case, no messages lost . . . . . . . . . . . . 514
Fig 86. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Fig 87. Message gets overwritten . . . . . . . . . . . . . . . . . 515
Chapter 36: LPC24XX Supplementary information
Dual-Role device, port U2 host . . . . . . . . . . . . . 397
host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
PORT_FUNC bit 1 = 0. . . . . . . . . . . . . . . . . . . . 404
peripheral state to host state . . . . . . . . . . . . . . 413
B-device switching from peripheral to host . . . . 414
state to peripheral state. . . . . . . . . . . . . . . . . . . 416
A-device switching from host to peripheral . . . . 417
frame format configurations . . . . . . . . . . . . . . . 470
frame format configurations . . . . . . . . . . . . . . . 471
example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
UM10237
© NXP B.V. 2009. All rights reserved.
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