LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 774

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Fig 88. Message overwritten indicated by semaphore bits
Fig 89. Message overwritten indicated by message lost517
Fig 90. Clearing message lost . . . . . . . . . . . . . . . . . . . .518
Fig 91. Detailed example of acceptance filter tables and ID
Fig 92. ID Look-up table configuration example (no
Fig 93. ID Look-up table configuration example (FullCAN
Fig 94. SPI data transfer format (CPHA = 0 and
Fig 95. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .535
Fig 96. Texas Instruments Synchronous Serial Frame
Fig 97. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 98. SPI frame format with CPOL=0 and CPHA=1 . .540
Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 100. SPI Frame Format with CPOL = 1 and
Fig 101. Microwire frame format (single transfer) . . . . . .543
Fig 102. Microwire frame format (continuos transfers) . .544
Fig 103. Microwire frame format setup and hold details .544
Fig 104. Multimedia card system . . . . . . . . . . . . . . . . . . .552
Fig 105. Secure digital memory card connection. . . . . . .553
Fig 106. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
Fig 107. Command path state machine . . . . . . . . . . . . . .555
Fig 108. MCI command transfer . . . . . . . . . . . . . . . . . . .555
Fig 109. Data path state machine . . . . . . . . . . . . . . . . . .558
Fig 110. Pending command start . . . . . . . . . . . . . . . . . . .560
Fig 111. I
Fig 112. Format in the Master Transmitter mode. . . . . . .575
Fig 113. Format of Master Receive mode . . . . . . . . . . . .575
Fig 114. A master receiver switch to master Transmitter after
Fig 115. Format of Slave Receiver mode . . . . . . . . . . . .576
Fig 116. Format of Slave Transmitter mode . . . . . . . . . .577
Fig 117. I
Fig 118. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .579
Fig 119. Serial clock synchronization. . . . . . . . . . . . . . . .580
Fig 120. Format and States in the Master Transmitter
Fig 121. Format and States in the Master Receiver
Fig 122. Format and States in the Slave Receiver mode.592
Fig 123. Format and States in the Slave Transmitter
Fig 124. Simultaneous repeated START conditions from 2
Fig 125. Forced access to a busy I
Fig 126. Recovering from a bus obstruction caused by a low
Fig 127. Simple I2S configurations and bus timing . . . . .613
Fig 128. FIFO contents for various I
Fig 129. A timer cycle in which PR=2, MRx=6, and both
UM10237_4
User manual
and message lost. . . . . . . . . . . . . . . . . . . . . . . .516
index values. . . . . . . . . . . . . . . . . . . . . . . . . . . .520
FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522
activated and enabled) . . . . . . . . . . . . . . . . . . .524
CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .538
Single and b) Continuous Transfer) . . . . . . . . . .539
Single and b) Continuous Transfer) . . . . . . . . . .541
CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
sending repeated START. . . . . . . . . . . . . . . . . .576
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .591
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601
level on SDA . . . . . . . . . . . . . . . . . . . . . . . . . . .602
2
2
C bus configuration . . . . . . . . . . . . . . . . . . . . .573
C Bus serial interface block diagram. . . . . . . .578
2
C bus . . . . . . . . . . . .602
2
S modes. . . . . . . . .620
Rev. 04 — 26 August 2009
Fig 130. A timer Cycle in Which PR=2, MRx=6, and both
Fig 131. Timer block diagram . . . . . . . . . . . . . . . . . . . . . 631
Fig 132. PWM block diagram . . . . . . . . . . . . . . . . . . . . . 634
Fig 133. Sample PWM waveforms . . . . . . . . . . . . . . . . . 636
Fig 134. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . 648
Fig 135. RTC prescaler block diagram . . . . . . . . . . . . . . 658
Fig 136. RTC 32 kHz crystal oscillator circuit . . . . . . . . . 660
Fig 137. Watchdog block diagram. . . . . . . . . . . . . . . . . . 666
Fig 138. Map of lower memory after reset . . . . . . . . . . . 677
Fig 139. Boot process flowchart . . . . . . . . . . . . . . . . . . . 680
Fig 140. IAP parameter passing . . . . . . . . . . . . . . . . . . . 692
Fig 141. Map of lower memory after reset for flashless
Fig 142. Boot process flowchart . . . . . . . . . . . . . . . . . . . 700
Fig 143. IAP parameter passing . . . . . . . . . . . . . . . . . . . 708
Fig 144. GPDMA block diagram . . . . . . . . . . . . . . . . . . . 713
Fig 145. GPDMA in the LPC24XX . . . . . . . . . . . . . . . . . 714
Fig 146. LLI example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Fig 147. EmbeddedICE debug environment block
Fig 148. ETM debug environment block diagram . . . . . . 747
Fig 149. RealMonitor components . . . . . . . . . . . . . . . . . 749
Fig 150. RealMonitor as a State Machine . . . . . . . . . . . . 750
Fig 151. Exception handlers. . . . . . . . . . . . . . . . . . . . . . 753
Chapter 36: LPC24XX Supplementary information
interrupt and reset on match are enabled. . . . . 630
interrupt and stop on match are enabled . . . . . 630
LPC2400 parts . . . . . . . . . . . . . . . . . . . . . . . . . 698
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
UM10237
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