LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 787

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
6.7
6.8
6.9
6.10
Chapter 22: LPC24XX I
1
2
3
4
5
6
6.1
6.2
6.3
6.4
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
9.1
9.2
9.3
9.4
9.5
22.9.5.1
UM10237_4
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 572
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 574
I
I
Register description . . . . . . . . . . . . . . . . . . . 581
Details of I
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 574
C implementation and operation . . . . . . . . 577
Data Timer Register (MCIDataTimer -
0xE008 C024). . . . . . . . . . . . . . . . . . . . . . . . 567
Data Length Register (MCIDataLength -
0xE008 C028). . . . . . . . . . . . . . . . . . . . . . . . 567
Data Control Register (MCIDataCtrl -
0xE008 C02C) . . . . . . . . . . . . . . . . . . . . . . . 568
Data Counter Register (MCIDataCnt -
0xE008 C030). . . . . . . . . . . . . . . . . . . . . . . . 568
Master Transmitter mode . . . . . . . . . . . . . . . 574
Master Receiver mode . . . . . . . . . . . . . . . . . 575
Slave Receiver mode . . . . . . . . . . . . . . . . . . 576
Slave Transmitter mode . . . . . . . . . . . . . . . . 577
Input filters and output stages. . . . . . . . . . . . 577
Address Register I2ADDR . . . . . . . . . . . . . . 579
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 579
Shift register I2DAT. . . . . . . . . . . . . . . . . . . . 579
Arbitration and synchronization logic . . . . . . 579
Serial clock generator . . . . . . . . . . . . . . . . . . 580
Timing and control . . . . . . . . . . . . . . . . . . . . 580
Control register I2CONSET and I2CONCLR 580
Status decoder and status register . . . . . . . . 581
I
0xE001 C000, 0xE005 C000, 0xE008 0000) 582
I
0xE001 C018, 0xE005 C018, 0xE008 0018) 584
I
0xE001 C004, 0xE005 C004, 0xE008 0004) 584
I
0xE005 C008, 0xE008 0008) . . . . . . . . . . . . 585
I
0xE001 C00C, 0xE005 C00C, 0xE008 000C) 585
I
(I2C[0/1/2]SCLH - 0xE001 C010, 0xE005 C010,
0xE008 0010) . . . . . . . . . . . . . . . . . . . . . . . . 585
I
(I2C[0/1/2]SCLL - 0xE001 C014, 0xE005 C014,
0xE008 0014) . . . . . . . . . . . . . . . . . . . . . . . . 585
Selecting the appropriate I
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Master Transmitter mode . . . . . . . . . . . . . . . 587
Master Receiver mode . . . . . . . . . . . . . . . . . 588
Slave Receiver mode . . . . . . . . . . . . . . . . . . 588
Slave Transmitter mode . . . . . . . . . . . . . . . . 593
Miscellaneous states . . . . . . . . . . . . . . . . . . 599
I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 599
2
2
2
2
2
2
2
C Control Set Register (I2C[0/1/2]CONSET:
C Control Clear Register (I2C[0/1/2]CONCLR:
C Status Register (I2C[0/1/2]STAT -
C Data Register (I2C[0/1/2]DAT - 0xE001 C008,
C Slave Address Register (I2C[0/1/2]ADR -
C SCL High Duty Cycle Register
C SCL Low Duty Cycle Register
2
C operating modes. . . . . . . . . . . 586
2
C interfaces I
2
C data rate and duty
2
C0/1/2
Rev. 04 — 26 August 2009
6.11
6.12
6.13
6.14
6.15
22.9.5.2
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
10
10.1
10.2
10.3
10.4
10.5
10.5.1
10.6
10.6.1
10.6.2
10.7
10.7.1
10.7.2
10.7.3
10.7.4
10.7.5
10.8
10.8.1
10.8.2
10.8.3
10.8.4
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
10.9.7
10.9.8
10.9.9
10.10
10.10.1
Chapter 36: LPC24XX Supplementary information
Software example . . . . . . . . . . . . . . . . . . . . . 603
Status Register (MCIStatus - 0xE008 C034) 569
Clear Register (MCIClear - 0xE008 C038) . 570
Interrupt Mask Registers (MCIMask0 -
0xE008 C03C) . . . . . . . . . . . . . . . . . . . . . . . 570
FIFO Counter Register (MCIFifoCnt -
0xE008 C048) . . . . . . . . . . . . . . . . . . . . . . . 571
Data FIFO Register (MCIFIFO - 0xE008 C080 to
0xE008 C0BC) . . . . . . . . . . . . . . . . . . . . . . . 571
I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 599
Some special cases . . . . . . . . . . . . . . . . . . . 600
Simultaneous repeated START conditions from
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 600
Data transfer after loss of arbitration . . . . . . 600
Forced access to the I
I
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
I
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 602
I
The state service routines . . . . . . . . . . . . . . 603
Adapting state services to an application. . . 603
Initialization routine . . . . . . . . . . . . . . . . . . . 603
Start master transmit function . . . . . . . . . . . 603
Start master receive function . . . . . . . . . . . . 603
I
Non mode specific states. . . . . . . . . . . . . . . 604
State : 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . 604
Master states . . . . . . . . . . . . . . . . . . . . . . . . 604
State : 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . 604
State : 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . 604
Master Transmitter states . . . . . . . . . . . . . . 605
State : 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . 605
State : 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . 605
State : 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . 605
State : 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . 605
State : 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . 606
Master Receive states . . . . . . . . . . . . . . . . . 606
State : 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . 606
State : 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . 606
State : 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . 606
State : 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . 606
Slave Receiver states . . . . . . . . . . . . . . . . . 607
State : 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . 607
State : 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . 607
State : 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . 607
State : 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . 607
State : 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . 608
State : 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . 608
State : 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . 608
State : 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . 608
State : 0xA0 . . . . . . . . . . . . . . . . . . . . . . . . . 608
Slave Transmitter States . . . . . . . . . . . . . . . 609
State : 0xA8 . . . . . . . . . . . . . . . . . . . . . . . . . 609
2
2
2
2
C Bus obstructed by a Low level on SCL or
C State service routines. . . . . . . . . . . . . . . 602
C interrupt service . . . . . . . . . . . . . . . . . . . 603
C interrupt routine . . . . . . . . . . . . . . . . . . . 604
2
C bus. . . . . . . . . . . . 600
UM10237
© NXP B.V. 2009. All rights reserved.
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