LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 81

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh -
0xFFE0 8024)
The EMCDynamicRefresh register configures dynamic memory operation. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. However, these control bits can, if
necessary, be altered during normal operation. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
assignments for the EMCDynamicRefresh register.
Table 72.
For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wakeup period of a reset cycle. During this period, the
EMC (and all other portions of the LPC2400 that are being clocked) run from the IRC
oscillator at 4 MHz. So, 4 MHz must be considered the CCLK rate for refresh calculations
if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
Bit
10:0
31:11 -
Symbol
Refresh timer
(REFRESH)
Dynamic Memory Refresh Timer register (EMCDynamicRefresh - address
0xFFE0 8024) bit description
Rev. 04 — 26 August 2009
Value Description
0x0
0x1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Indicates the multiple of 16 CCLKs between SDRAM
refresh cycles.
Refresh disabled (POR reset value).
0x7FF = n x16 = 16n CCLKs between SDRAM refresh
cycles.
For example:
0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh
cycles.
0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh
cycles.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Table 5–72
UM10237
shows the bit
© NXP B.V. 2009. All rights reserved.
81 of 792
Reset
Value
0
NA