ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet

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MCU with single voltage Flash memory, ADC, timers Features ■ Memories – 1 Kbytes single-voltage Flash Program memory with readout protection, ICP and IAP write/erase cycles guaranteed data retention: 20 years at 55 °C – 128 bytes ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITEUS2, ST7LITEUS5 6.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 8.5.1 9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITEUS2, ST7LITEUS5 11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 12.8.1 12.8.2 12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITEUS2, ST7LITEUS5 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 49. Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 96 Table 50. Internal ...

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ST7LITEUS2, ST7LITEUS5 List of figures Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 48. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITEUS2, ST7LITEUS5 1 Introduction The ST7LITEUS2 and ST7LITEUS5 are members of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITEUS2 and ST7LITEUS5 feature FLASH memory with byte-by-byte ...

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Pin description 2 Pin description Figure 2. 8-pin SO and Plastic DIP package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3/MCO 1. HS: High sink capability. 2. eix : associated external interrupt vector Figure 3. 8-pin DFN ...

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ST7LITEUS2, ST7LITEUS5 Figure 4. 16-pin package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3/MCO 1. Reserved pins must be tied to ground. 2. The differences versus the 8-pin packages are listed below: 2 The I C signals ...

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Pin description Legend/abbreviations for Type input output supply In/Output level Output level High sink (on N-buffer only) Port and control configuration ● Input: float = floating, wpu = weak pull-up, ...

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ST7LITEUS2, ST7LITEUS5 3 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes up to ...

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Register and memory map Table 3. Hardware register map Register Address Block label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h- 000Ah 000Bh LITE LTCSR 000Ch TIMER LTICR 000Dh ATCSR 000Eh CNTRH 000Fh AUTO- CNTRL 0010h RELOAD ATRH 0011h ...

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ST7LITEUS2, ST7LITEUS5 Table 3. Hardware register map (continued) Register Address Block label 0049h AWUPR AWU 004Ah AWUCSR 004Bh DMCR 004Ch DMSR 004Dh DMBK1H (4) DM 004Eh DMBK1L 004Fh DMBK2H 0050h DMBK2L 0051h to 007Fh 1. Legend: x=undefined, R/W=read/write 2. The ...

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Flash program memory 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The ...

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ST7LITEUS2, ST7LITEUS5 2 the I C protocol routine. This routine enables the ST7 to receive bytes from the I interface. ● Download ICP driver code in RAM from the ICCDATA pin ● Execute ICP driver code in RAM to program ...

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Flash program memory Pin 9 has to be connected to the CLKIN pin of the ST7 when I option bytes disabled (35-pulse entry mode), the internal RC clock (internal RC or AWU RC) is forced. If ...

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ST7LITEUS2, ST7LITEUS5 In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. Readout protection selection depends on the device type: ● In Flash devices it ...

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Flash program memory 4.7 Register description 4.7.1 Flash Control/Status register (FCSR) This register controls the XFlash erasing and programming using ICP, IAP or other programming methods. 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an ...

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ST7LITEUS2, ST7LITEUS5 5 Central processing unit 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● ...

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Central processing unit Figure 7. CPU registers PCH 15 RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE = 1 15 RESET VALUE = STACK HIGHER ADDRESS Undefined value 5.3.4 Condition Code register (CC) The 8-bit Condition ...

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ST7LITEUS2, ST7LITEUS5 Bit 7:5 Set to ‘1’ Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction reset by ...

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Central processing unit 5.3.5 Stack Pointer (SP) Reset value: 00 FFh The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented ...

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ST7LITEUS2, ST7LITEUS5 Figure 8. Stack manipulation example CALL subroutine @ 00C0h SP SP PCH PCL @ 00FFh 1. Stack higher address = 00FFh. 2. Stack lower address = 00C0h. PUSH Y POP Y Interrupt event ...

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Supply, reset and clock management 6 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external ...

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ST7LITEUS2, ST7LITEUS5 2 Note mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note See Section 12: Electrical characteristics accuracy of ...

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Supply, reset and clock management Figure 9. Clock switching 6.3 Register description 6.3.1 Main Clock Control/Status register (MCCSR) Reset value: 0000 0000 (00h Bits 7:2 Reserved, must be kept cleared. Bit 1 MCO Main Clock Out enable ...

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ST7LITEUS2, ST7LITEUS5 6.3.2 RC Control register (RCCR) Reset value: 1111 1111 (FFh) 7 CR9 CR8 Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset ...

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Supply, reset and clock management 6.3.4 AVD Threshold Selection register (AVDTHCR) Reset value: 0000 0011 (03h) 7 CK2 CK1 Bits 7:5 CK[2:0] Internal RC Prescaler Selection These bits are set by software and cleared by hardware after a reset. These ...

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ST7LITEUS2, ST7LITEUS5 Bit 2 RC_FLAG RC Selection This bit is set and cleared by hardware 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared. Bit 0 ...

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Supply, reset and clock management Figure 10. Clock management block diagram CR9 CR8 Tunable internal RC Prescaler CLKIN f CLKIN f OSC /32 DIVIDER 34/136 RCCR CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Oscillator Clock 8MHz Controller ...

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ST7LITEUS2, ST7LITEUS5 6.4 Reset sequence manager (RSM) 6.4.1 Introduction The reset sequence manager includes three reset sources as shown in ● External RESET source pulse ● Internal LVD reset (low voltage detection) ● Internal WATCHDOG reset Note: A reset can ...

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Supply, reset and clock management Figure 12. Reset block diagram RESET 1. Section 11.2.1: Illegal opcode reset 6.4.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has ...

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ST7LITEUS2, ST7LITEUS5 6.4.5 Internal watchdog reset The reset sequence generated by a internal watchdog counter overflow is shown in Figure 13. Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during ...

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Supply, reset and clock management This 16-bit register is read/write by software but can be written only once between two reset events cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the ...

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ST7LITEUS2, ST7LITEUS5 7 Interrupts The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...

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Interrupts 7.2 External interrupts External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The ...

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ST7LITEUS2, ST7LITEUS5 Table 9. Interrupt mapping N° Source block RESET Reset TRAP Software interrupt 0 AWU Auto-wakeup interrupt 1 ei0 External interrupt 0 2 ei1 External interrupt 1 3 ei2 External interrupt 2 4 Not used 5 ei3 External interrupt ...

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Interrupts Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted ...

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ST7LITEUS2, ST7LITEUS5 7.4 System integrity management (SI) The System Integrity Management block contains the low voltage detector (LVD) and Auxiliary Voltage Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the ...

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Interrupts Figure 15. Low voltage detector vs reset IT+ (LVD) V IT- (LVD) RESET Figure 16. Reset and supply management block diagram RESET SEQUENCE RESET 44/136 V hys WATCHDOG TIMER (WDG) SYSTEM INTEGRITY ...

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ST7LITEUS2, ST7LITEUS5 7.4.2 Auxiliary voltage detector (AVD) The voltage detector function (AVD) is based on an analog comparison between a V and V reference value and the V IT+(AVD) reference value for falling voltage is lower than the V voltage ...

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Interrupts 7.4.3 Low power modes Table 11. Description of low power modes Mode Wait Halt Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register ...

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ST7LITEUS2, ST7LITEUS5 Bit 2 LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block set by hardware (LVD reset) and cleared when read. See WDGRF flag description in Section 10.1.6 on ...

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Power saving modes 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and ...

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ST7LITEUS2, ST7LITEUS5 8.2 Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (f Slow mode is controlled by the SMS bit in ...

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Power saving modes Figure 20. Wait mode flowchart 1. 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC ...

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ST7LITEUS2, ST7LITEUS5 8.4.1 Active-halt mode Active-halt mode is the lowest power consumption mode of the MCU with a real time clock available entered by executing the ‘HALT’ instruction when Active-halt mode is enabled. The MCU can exit Active-halt ...

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Power saving modes Figure 22. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-halt mode by means of a reset. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite ...

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ST7LITEUS2, ST7LITEUS5 Figure 23. Halt timing overview 1. A reset pulse of at least 42µs must be applied when exiting from Halt mode. Figure 24. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more ...

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Power saving modes Halt mode recommendations ● Make sure that an external event is available to wakeup the microcontroller from Halt mode. ● When using an external interrupt to wakeup the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with ...

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ST7LITEUS2, ST7LITEUS5 After this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC ...

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Power saving modes Figure 27. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some ...

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ST7LITEUS2, ST7LITEUS5 8.5.1 Register description AWUFH Control/ Status register (AWUCSR) Reset value: 0000 0000 (00h Bits 7:3 Reserved Bit 2 AWUF Auto-wakeup Flag This bit is set by hardware when the AWU module generates an interrupt and ...

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Power saving modes Table 15. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh In AWU mode, the period that the MCU stays in Halt Mode (t This prescaler register can be programmed to modify the time that the ...

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ST7LITEUS2, ST7LITEUS5 9 I/O ports 9.1 Introduction The I/O port offers different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins: ● External interrupt generation ● Alternate signal input/output for the on-chip peripherals. An ...

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I/O ports Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge ...

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ST7LITEUS2, ST7LITEUS5 9.2.3 Alternate functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions: ● When the signal is ...

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I/O ports Table 18. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without Interrupt Push-pull Output Open Drain (logic level stands for not implemented; Off for implemented not activated; On for implemented and activated. Table ...

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ST7LITEUS2, ST7LITEUS5 Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, ...

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I/O ports 9.6 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these ...

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ST7LITEUS2, ST7LITEUS5 10 On-chip peripherals 10.1 Lite timer (LT) 10.1.1 Introduction The Lite Timer can be used for general-purpose timing functions based on a free- running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register ...

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On-chip peripherals Figure 30. Lite timer block diagram f OSC 13-bit UPCOUNTER LTICR LTIC INPUT CAPTURE REGISTER 10.1.3 Functional description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing ...

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ST7LITEUS2, ST7LITEUS5 A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to ...

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On-chip peripherals 10.1.4 Low power modes Table 24. Description of low power modes Mode Wait Active-Halt Halt 10.1.5 Interrupts Table 25. Interrupt events Interrupt event Timebase Event IC Event 1. The TBF and ICF interrupt events are connected to separate ...

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ST7LITEUS2, ST7LITEUS5 10.1.6 Register description Lite timer control/status register (LTCSR) Reset value: 0000 0x00 (0xh) 7 ICIE ICF Bit 7 ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture ...

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On-chip peripherals Bit 2 WDGRF Force Reset/ Reset Status Flag This bit is used in two ways set by software to force a watchdog reset set by hardware when a watchdog reset occurs and cleared by ...

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ST7LITEUS2, ST7LITEUS5 10.2 12-bit auto-reload timer (AT) 10.2.1 Introduction The 12-bit auto-reload timer can be used for general-purpose timing functions based on a free-running 12-bit upcounter with a PWM output channel. 10.2.2 Main features ● 12-bit upcounter with ...

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On-chip peripherals PWM frequency and duty cycle The PWM signal frequency (f value PWM COUNTER Following the above formula register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). ...

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ST7LITEUS2, ST7LITEUS5 Figure 35. PWM signal example f COUNTER COUNTER DCR0=FFEh Output compare mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must ...

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On-chip peripherals 10.2.5 Interrupts Table 28. Interrupt events Interrupt event Overflow event CMP event 1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR ...

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ST7LITEUS2, ST7LITEUS5 Table 29. Counter clock selection Counter register high (CNTRH) Reset value: 0000 0000 (00h Counter register low (CNTRL) This 12-bit register is read by software and cleared by hardware after a reset. The counter is ...

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On-chip peripherals Auto reload register (ATRL) This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency. ...

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ST7LITEUS2, ST7LITEUS5 PWM0 control/status register (PWM0CSR) Reset value: 0000 0000 (00h Bit 7:2 Reserved, must be kept cleared. Bit 1 OP0 PWM0 output polarity. This bit is read/write by software and cleared by hardware after a reset. ...

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On-chip peripherals Table 30. Register map and reset values (continued) Address Register label (Hex.) ATRL 11 Reset value PWMCR 12 Reset value PWM0CSR 13 Reset value DCR0H 17 Reset value DCR0L 18 Reset value 78/136 ATR7 ...

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ST7LITEUS2, ST7LITEUS5 10.3 10-bit A/D converter (ADC) 10.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...

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On-chip peripherals Figure 36. ADC block diagram f CPU DIV 2 AIN0 AIN1 ANALOG MUX AINx Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if ...

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ST7LITEUS2, ST7LITEUS5 cycles) and the C the optimum analog to digital conversion accuracy. ● The total conversion time CONV = SAMPLE While the ADC is on, these two phases are continuously repeated. At the end of each conversion, ...

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On-chip peripherals 10.3.5 Interrupts None. 10.3.6 Register description Control/Status register (ADCCSR) Reset value: 0000 0000 (00h) 7 EOC SPEED Bit 7 EOC End of Conversion This bit is set by hardware cleared by software reading the ADCDRH register. ...

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ST7LITEUS2, ST7LITEUS5 ADC data register high (ADCDRH) Reset value: 0000 0000 (00h Bits 7:0 D[9:2] MSB of Analog Converted value ADC control/data register Low (ADCDRL) Reset value: 0000 0000 (00h Bits 7:4 Reserved. Forced ...

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Instruction set 11 Instruction set 11.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Table 35. Description of addressing modes Addressing mode Bit operation The ST7 instruction set is ...

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ST7LITEUS2, ST7LITEUS5 Table 36. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the Program Counter (PC) points ...

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Instruction set 11.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Table 38. Instructions supporting inherent immediate addressing mode Immediate instruction AND, OR, XOR ADC, ADD, SUB, SBC 11.1.3 ...

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ST7LITEUS2, ST7LITEUS5 11.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect ...

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Instruction set Table 39. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Instructions BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC 11.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register ...

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ST7LITEUS2, ST7LITEUS5 Table 41. ST7 instruction set (continued) Shift and rotates Unconditional jump or call Conditional branch Interruption management Condition code flag modification Using a prebyte The instructions are described with bytes. In order to extend the ...

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Instruction set Table 42. Illegal opcode detection (continued) Mnemo Description BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative CLR Clear CP ...

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ST7LITEUS2, ST7LITEUS5 Table 42. Illegal opcode detection (continued) Mnemo Description NEG Negate (2's compl) NOP No operation OR OR operation POP Pop from the stack PUSH Push onto the stack RCF Reset carry flag RET Subroutine return RIM Enable Interrupts ...

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Electrical characteristics 12 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

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ST7LITEUS2, ST7LITEUS5 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 38. Pin input voltage 12.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage ...

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Electrical characteristics Table 44. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly insured if V ...

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ST7LITEUS2, ST7LITEUS5 Figure 39. f CPU f [MHz] CPU 8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2.0 12.3.2 Operating conditions with low voltage detector (LVD -40 to 125 °C, unless otherwise specified A Table 47. ...

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Electrical characteristics 12.3.3 Auxiliary voltage detector (AVD) thresholds = −40 to 125°C, unless otherwise specified Table 48. Operating characteristics with AVD Symbol 1 => 0 AVDF flag toggle threshold V IT+ (AVD) 0 => 1 AVDF flag toggle ...

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ST7LITEUS2, ST7LITEUS5 Table 50. Internal RC oscillator characteristics (5.0 V calibration) Symbol Parameter Internal RC oscillator f RC frequency Accuracy of internal RC ACC oscillator with RC (1) RCCR=RCCR0 t RC oscillator setup time su(RC) 1. See Section 6.2: Internal ...

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Electrical characteristics Figure 40. Typical accuracy with RCCR=RCCR0 vs V 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 Figure 41. Typical accuracy with RCCR=RCCR1 vs ...

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ST7LITEUS2, ST7LITEUS5 12.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values ...

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Electrical characteristics 12.4.2 Internal RC oscillator supply current characteristics Table 53. Internal RC oscillator supply current Symbol Parameter Supply current in Run mode Supply current in Wait mode I DD Supply current in Slow mode Supply current in Slow-Wait (5) ...

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ST7LITEUS2, ST7LITEUS5 Figure 42. Typical I Figure 43. Typical I Figure 44. Typical MHz in run mode vs. internal clock frequency and V DD Idd RUN m ode @ int clock freq RC ...

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Electrical characteristics Figure 45 temp @V DD Figure 46 temp @V DD Figure 47 temp @V DD 102/136 5 V & int MHz DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 ...

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ST7LITEUS2, ST7LITEUS5 12.4.3 On-chip peripherals Table 54. On-chip peripheral characteristics Symbol Parameter I 12-bit auto-reload timer supply current DD(AT) I ADC supply current when converting DD(ADC) 1. Not tested in production, guaranteed by characterization. 2. Data based on a differential ...

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Electrical characteristics 12.6 Memory characteristics T = -40 to 125 °C, unless otherwise specified; A Table 57. RAM and Hardware registers Symbol V Data retention mode RM Table 58. Flash Program memory Symbol Operating voltage for Flash V DD write/erase ...

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ST7LITEUS2, ST7LITEUS5 12.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...

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Electrical characteristics 12.7.2 Electromagnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...

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... Static latchup class DLU Dynamic latchup class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...

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Electrical characteristics 12.8 I/O port pin characteristics 12.8.1 General characteristics Subject to general operating conditions for V Table 63. General characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys ...

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ST7LITEUS2, ST7LITEUS5 Figure 49. Typical I 12.8.2 Output driving current characteristics Subject to general operating conditions for V Table 64. Output driving current characteristics Symbol Parameter Output low level voltage for PA3/RESET standard I/O pin (see Figure 52) (1) V ...

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Electrical characteristics Figure 50. Typical V Figure 51. Typical V Figure 52. Typical V 110/136 2.4 V (standard pins 1400 -45°C 1200 25°C 1000 90°C 800 130°C 600 400 200 Iol [mA] ...

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ST7LITEUS2, ST7LITEUS5 Figure 53. Typical V 1200 1000 Figure 54. Typical V Figure 55. Typical 2.4 V (HS pins -45°C 25°C 90°C 800 130°C 600 400 200 Iol ...

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Electrical characteristics Figure 56. Typical V 1800 1600 1400 1200 1000 800 600 400 200 Figure 57. Typical V Figure 58. Typical V 1000 112/136 - 2.4 V (HS pins -45°C 25°C 90°C 130°C ...

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ST7LITEUS2, ST7LITEUS5 Figure 59. Typical V 100 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Figure 60. Typical V 200 180 160 140 120 100 2.4 2.6 2.8 3 3.2 3.4 ...

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Electrical characteristics Refer also to Section 11.2.1: Illegal opcode reset conditions. Table 65. Asynchronous RESET pin characteristics Symbol V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys hysteresis V Output low level ...

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ST7LITEUS2, ST7LITEUS5 Figure 62. RESET pin protection when LVD is disabled USER EXTERNAL RESET CIRCUIT Required 12.10 ADC characteristics Subject to general operating condition for V Table 66. 10-bit ADC characteristics Symbol f ADC clock frequency ADC V Conversion voltage ...

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Electrical characteristics Figure 63. Typical application with ADC V AIN Table 67. ADC accuracy with V Symbol ( Total unadjusted error Offset error Gain Error Differential linearity error D ...

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ST7LITEUS2, ST7LITEUS5 Figure 64. ADC accuracy characteristics Digital Result ADCDR 1023 1022 1021 1. Example of an actual transfer curve 2. The ideal transfer curve 3. End point correlation line 4. E =Total Unadjusted Error: maximum deviation between the actual ...

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Package characteristics 13 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

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ST7LITEUS2, ST7LITEUS5 Figure 66. 8-pin plastic small outline package, 150-mil width package outline Table 71. 8-pin plastic small outline package, 150-mil width, package mechanical data Dim α ...

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Package characteristics Figure 67. 8-pin plastic dual in-line package, 300-mil width package outline Table 72. 8-pin plastic dual in-line package, 300-mil width package mechanical data Dim ...

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ST7LITEUS2, ST7LITEUS5 Figure 68. 16-pin plastic dual in-line package, 300-mil width, package outline Table 73. 16-pin plastic dual in-line package, 300-mil width, package mechanical data Dim 18. ...

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Package characteristics 13.2 Thermal characteristics Table 74. Thermal characteristics Symbol Package thermal resistance R thJA (junction to ambient) Maximum junction T Jmax temperature P Power dissipation Dmax 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum ...

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ST7LITEUS2, ST7LITEUS5 14 Device configuration and ordering information Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). Refer to numbers: ● ST7FLITEUSA2xx and ST7FLITEUSA5xx XFlash devices are shipped to customers ...

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Device configuration and ordering information Table 75. Startup clock selection Internal RC as Startup Clock Reserved AWU Startup Clock Reserved External Clock on pin PA5 Table 76. LVD threshold configuration LVD Off Highest voltage threshold Medium voltage ...

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... FFh. The selected options are communicated to STMicroelectronics using the correctly completed option list appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 79. Supported order codes ...

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Device configuration and ordering information Table 79. Supported order codes Program Order code memory (bytes) ST7PLUSA5B6 ST7PLUSA5M6 1 Kbyte ST7PLUSA5M6TR FASTROM ST7PLUSA5U6 ST7PLUSA5U6TR ST7PLUSA2B3 ST7PLUSA2M3 1 Kbyte FLASH ST7PLUSA2M3TR ST7PLUSA2U3TR ST7PLUSA5B3 ST7PLUSA5M3 1 Kbyte ST7PLUSA5M3TR FLASH ST7PLUSA5U3 ST7PLUSA5U3TR ST7PLUSA2B3 ST7PLUSA2M3 ...

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... Phone No Reference/FASTROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . . *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ...

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... Development tools Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. ...

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ST7LITEUS2, ST7LITEUS5 Table 80. Development tool order codes for the ST7LITEUSx family In-circuit Debugger, RLink series Supported Starter kit products without demo board ST7FLITEUS2 (2) STX-RLINK ST7FLITEUS5 1. Available from ST or from Raisonance, www.raisonance.com. 2. USB connection to PC. ...

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Device configuration and ordering information Table 81. ST7 application notes (continued) Identification AN1044 Multiple interrupt sources management for ST7 MCUs AN1045 ST7 S/W implementation of I²C bus master AN1046 UART emulation software AN1047 Managing reception errors with the ST7 SCI ...

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ST7LITEUS2, ST7LITEUS5 Table 81. ST7 application notes (continued) Identification AN1077 Overview of enhanced CAN controllers for ST7 and ST9 MCUs AN1086 U435 can-do solutions for car multiplexing AN1103 Improved B-EMF detection for low speed, low voltage with ST72141 AN1150 Benchmark ...

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Device configuration and ordering information Table 81. ST7 application notes (continued) Identification AN 987 ST7 serial test controller programming AN 988 Starting with ST7 assembly tool chain AN1039 ST7 math utility routines AN1071 Half duplex USB-to-serial bridge using the ST72611 ...

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ST7LITEUS2, ST7LITEUS5 15 Known limitations External interrupt 2 (ei2) Whatever the external interrupt sensitivity configured through EICR1 register, ei2 cannot exit the MCU from Halt, Active-halt and AWUFH modes when a falling edge occurs. Workaround None Known limitations 133/136 ...

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Revision history 16 Revision history Table 82. Document revision history Date Revision 06-Feb-06 1 18-Apr-06 2 134/136 Initial release Removed references Added note below Figure 4 Modified presentation of Section 4.3.1 Added notes to Section 6.2 (above ...

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ST7LITEUS2, ST7LITEUS5 Table 82. Document revision history (continued) Date Revision 18-Sep-06 3 26-Jan-07 4 06-Feb-2009 5 Modified description of AVD[1:0] bits in the AVDTRH register in Modified description of CNTR[11:0] bits in Modified values in Table 44 LVD and AVD ...

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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...