IC ENCORE MCU FLASH 2K 28SOIC

 

Z8F0213SJ005EG

Manufacturer Part NumberZ8F0213SJ005EG
DescriptionIC ENCORE MCU FLASH 2K 28SOIC
ManufacturerZilog
SeriesEncore!® XP®
Z8F0213SJ005EG datasheets

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Warranty: 60 days

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Specifications of Z8F0213SJ005EG

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size512 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-SOIC (7.5mm Width)Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Other names269-4054
Z8F0213SJ005EG
  
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Download datasheet (4Mb)Embed
PrevNext
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in
when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the final Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data
Register before the previous character is completely transmitted) the DE signal is not
deasserted between characters. The
polarity of the Driver Enable signal.
1
DE
0
Idle State
of Line
lsb
1
Start
Bit0
Bit1
0
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1
---------------------------------------- -
Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
PS024314-0308
Figure
14. The Driver Enable signal asserts
bit in the UART Control Register 1 sets the
DEPOL
Data Field
Bit2
Bit3
Bit4
Bit5
Bit6
DE to Start Bit Setup Time (s)
Universal Asynchronous Receiver/Transmitter
®
Z8 Encore! XP
F0823 Series
Product Specification
Stop Bit
msb
Bit7
Parity
1
2
---------------------------------------- -
Baud Rate (Hz)
101