IC ENCORE MCU FLASH 2K 28SOIC

 

Z8F0213SJ005EG

Manufacturer Part NumberZ8F0213SJ005EG
DescriptionIC ENCORE MCU FLASH 2K 28SOIC
ManufacturerZilog
SeriesEncore!® XP®
Z8F0213SJ005EG datasheets

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Warranty: 60 days

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Specifications of Z8F0213SJ005EG

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size512 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-SOIC (7.5mm Width)Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Other names269-4054
Z8F0213SJ005EG
  
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Software Compensation Procedure
The value read from the ADC high and low byte registers are uncompensated. The user
mode software must apply gain and offset correction to this uncompensated value for
maximum accuracy. The following formula yields the compensated value:
(
ADC comp
=
ADC uncomp OFFCAL
where GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and
ADC
is the uncompensated value read from the ADC. The OFFCAL value is in
uncomp
two’s complement format, as are the compensated and uncompensated ADC values.
The offset compensation is performed first, followed by the gain compensation. One bit of
Note:
resolution is lost because of rounding on both the offset and gain computations. As a result
the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and
10 data bits. Also note that in the second term, the multiplication must be performed
before the division by 2
Caution:
Although the ADC can be used without the gain and offset compensation, it does exhibit
non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
ADC Control Register Definitions
The following sections define the ADC control registers.
ADC Control Register 0
The ADC Control register selects the analog input channel and initiates the
analog-to-digital conversion.
Table 72. ADC Control Register 0 (ADCCTL0)
BITS
7
6
CEN
REFSELL
FIELD
0
0
RESET
R/W
R/W
R/W
ADDR
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion is complete.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
PS024314-0308
)
(
(
+
ADC uncomp OFFCAL
16
. Otherwise, the second term evaluates to zero incorrectly.
5
4
3
REFEXT
CONT
0
0
0
R/W
R/W
R/W
F70H
®
Z8 Encore! XP
F0823 Series
Product Specification
) 2 16
) ∗ GAINCAL
2
1
0
ANAIN[3:0]
0
0
0
R/W
R/W
R/W
Analog-to-Digital Converter
122