Z8F0823PJ005SG Zilog, Z8F0823PJ005SG Datasheet
Z8F0823PJ005SG
Specifications of Z8F0823PJ005SG
Z8F0823PJ005SG
Related parts for Z8F0823PJ005SG
Z8F0823PJ005SG Summary of contents
Page 1
... High-Performance 8-Bit Microcontrollers Z8 Encore! Product Specification PS025203-0405 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: ® Z8F0823 Series 408.558.8300 • www.ZiLOG.com ...
Page 2
... Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded ...
Page 3
Revision History Each instance in Table 1 reflects a change to this document from its previous revi- sion. To see more detail, click the appropriate link in the table. Table 1. Revision History of this Document Revision Date Level April ...
Page 4
Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Reset and STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Port A–C Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 41 Port A–C Input Data Registers . . . . . ...
Page 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
... Trim Bit Address 0000H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Trim Bit Address 0001H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Trim Bit Address 0003H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Trim Bit Address 0004H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ZiLOG Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Operation ...
Page 10
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
List of Figures Figure 1. Z8 Encore! Figure 2. Z8F0823 and Z8F0813 in 8-Pin SOIC or PDIP Package Figure 3. Z8F0823 and Z8F0813 in 20-Pin SOIC, SSOP or PDIP ...
Page 12
Figure 27. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 13
List of Tables Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii ...
Page 14
Table 28. Port A–C Alternate Function Set 2 Sub-Registers (PxAFS2 Table 29. Port A–C Input Data Registers (PxIN ...
Page 15
Table 58. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . 82 Table 59. Watch-Dog Timer Control Register (WDTCTL ...
Page 16
Table 88. Flash Option Bits at Program Memory Address 0000H . . . . . . . . . . 135 Table 89. Flash Options Bits at Program Memory Address 0001H . . . . . . . . . ...
Page 17
Table 118. Analog-to-Digital Converter Electrical Characteristics and Timing. 181 Table 119. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 182 Table 120. GPIO ...
Page 18
... Power-On Reset (POR) • 2.7 to 3.6V operating voltage • thirteen 5V-tolerant input pins • 8-, 20- and 28-pin packages PS025203-0405 MCU family of products are the first in a line of ZiLOG ® Z8F0823 Series makes it suitable for a variety of applications ® Z8 Encore! Z8F0823 Series Product Specification ® ...
Page 19
Part Selection Guide Table 1 identifies the basic features and package styles available for each device within the ® Encore! Z8F0823 Series product line. Table 1. Z8 Encore! ...
Page 20
CPU Memory Busses Register Bus Timers UART Comparator IrDA GPIO Figure 1. Z8 Encore! PS025203-0405 System Oscillator Clock Control On-Chip Debugger Interrupt Controller ADC ® Z8F0823 Series Block Diagram ...
Page 21
... C-Compiler friendly • clock cycles per instruction For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail- able for download at www.zilog.com. General Purpose I/O ® The Z8 Encore! pose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable ...
Page 22
Internal Precision Oscillator The Internal Precision Oscillator (IPO trimmable clock source that requires no exter- nal components. 10-Bit Analog-to-Digital Converter The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10- bit binary number. The ADC ...
Page 23
On-Chip Debugger ® The Z8 Encore! (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writ- ing registers, programming Flash memory, setting breakpoints and executing code. A sin- gle-pin interface provides communication to the OCD. ...
Page 24
Pin Description Overview ® The Z8 Encore! and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information regarding the physical package specifica- tions, refer to the chapter Available Packages Table ...
Page 25
PA0/T0IN/T0OUT/DBG PA1/T0OUT/ANA3/VREF/CLKIN PA2/RESET/DE0/T1OUT Figure 2.Z8F0823 and Z8F0813 in 8-Pin SOIC or PDIP Package* PB1/ANA1 PB2/ANA2 PB3/CLKIN/ANA3 PA0/T0IN/T0OUT PA1/T0OUT PA2/DE0 PA3/CTS0 PA4/RXD0 Figure 3.Z8F0823 and Z8F0813 in 20-Pin SOIC, SSOP or PDIP Package* PB2/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 (PB6) AVDD PA0/T0IN/T0OUT PA1/T0OUT ...
Page 26
Signal Descriptions Table 3 describes the Z8 Encore! figurations” on page 7 Signal Mnemonic I/O Description General-Purpose I/O Ports A–D PA[7:0] I/O Port A. These pins are used for general-purpose I/O. PB[7:0] I/O Port B. These pins are used for ...
Page 27
Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description Analog ANA[7:0] I Analog Port. These signals are used as inputs to the analog-to-digital converter (ADC). The ANA0, ANA1 and ANA2 pins can also access the inputs and output of the ...
Page 28
Table 5 provides detailed information about the characteristics for each pin available on ® the Z8 Encore! Note: All six I/O pins on the 8-pin packages are 5V-tolerant (unless the pull-up devices are enabled). The column in Table 4 below ...
Page 29
Table 5. Pin Characteristics (8-Pin Devices) ) Symbol Reset Mnemonic Direction Direction PA0/DBG I/O I (but can change during reset if key sequence detected) PA1 I/O I RESET/ I/O I/O PA2 (defaults to RESET) PA[5:3] I/O I VDD N/A N/A ...
Page 30
... These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! ter File is composed of two sections: control registers and general-purpose registers ...
Page 31
Program Memory The eZ8 CPU supports 64KB of Program Memory address space. The Z8 Encore! Z8F0823 Series devices contain 8KB of on-chip Flash memory in the Program Memory address space. Reading from Program Memory addresses outside the available Flash memory ...
Page 32
... FE60–FE7F FE80–FFFF PS025203-0405 ® Z8F0823 Series Flash Memory Information Area Map Function ZiLOG Option Bits Part Number 20-character ASCII alphanumeric code Left justified and filled with FH Reserved ZiLOG Calibration Data Reserved ® Z8 Encore! Z8F0823 Series Product Specification Address Space 15 ...
Page 33
Register Map Table 8 provides the address map for the Register File of the Z8 Encore! Series devices. Not all devices and package styles in the Z8 Encore! support the ADC, or all of the GPIO Ports. Consider registers for ...
Page 34
Table 8. Register File Address Map (Continued) Address (Hex) Register Description F42 UART0 Control 0 F43 UART0 Control 1 F44 UART0 Status 1 F45 UART0 Address Compare F46 UART0 Baud Rate High Byte F47 UART0 Baud Rate Low Byte F48–F6F ...
Page 35
Table 8. Register File Address Map (Continued) Address (Hex) Register Description FC6 Interrupt Request 2 FC7 IRQ2 Enable High Bit FC8 IRQ2 Enable Low Bit FC9–FCC Reserved FCD Interrupt Edge Select FCE Shared Interrupt Select FCF Interrupt Control GPIO Port ...
Page 36
Table 8. Register File Address Map (Continued) Address (Hex) Register Description Flash Memory Controller FF8 Flash Control FF8 Flash Status FF9 Flash Page Select Flash Sector Protect FFA Flash Programming Frequency High Byte FFREQH FFB Flash Programming Frequency Low Byte ...
Page 37
Reset and STOP Mode Recovery Overview The Reset Controller within the Z8 Encore! Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset: • Power-On Reset (POR) • Voltage Brown-Out ...
Page 38
Table 9. Reset and STOP Mode Recovery Characteristics and Latency (Continued) Reset Type Control Registers STOP Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers STOP Mode Recovery with Unaffected, except Crystal Oscillator Enabled WDT_CTL and OSC_CTL registers During a System ...
Page 39
Table 10. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset / Voltage Brown- modes Out Watch-Dog Timer time-out when configured for Reset RESET pin assertion On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) ...
Page 40
V POR V VBO VCC = 0.0V Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Voltage Brown-Out Reset The devices in the Z8 Encore! protection. The VBO circuit senses when the supply voltage drops to an ...
Page 41
VCC = 3.3V V POR V VBO Program Execution WDT Clock System Clock Internal RESET signal Note: Not to Scale Figure 6.Voltage Brown-Out Reset Operation The POR level is greater than the VBO level by the specified hysteresis value. This ...
Page 42
A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! remain in ...
Page 43
Register is set to 1. Table 11 lists the STOP Mode Recovery sources and resulting actions. The text following provides more detailed information about each of the STOP Mode Recovery sources. Table 11. STOP Mode Recovery Sources and Resulting ...
Page 44
STOP Mode Recovery Using the External RESET Pin When the Z8 Encore! pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the Low pulse must be greater than the minimum width ...
Page 45
STOP Mode Recovery occurred because of a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset ...
Page 46
Low-Power Modes Overview ® The Z8 Encore! level of power reduction is provided by the STOP mode. The next lower level of power reduction is provided by the HALT mode. Further power savings can be implemented by disabling individual peripheral ...
Page 47
Primary oscillator is enabled and continues to operate • System clock is enabled and continues to operate • eZ8 CPU is stopped • Program counter (PC) stops incrementing • Watch-Dog Timer’s internal RC oscillator continues to operate • If ...
Page 48
Table 13. Power Control Register 0 (PWRCTL0) BITS 7 6 Reserved Reserved FIELD 1 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. VBO—Voltage Brown-Out Detector Disable This bit and the VBO_AO Flash option bit must both enable the VBO ...
Page 49
General-Purpose I/O Overview ® The Z8 Encore! D) for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, STOP Mode Recovery functionality, and alternate pin ...
Page 50
System Port Output Data Register DATA D Q Bus System Clock Figure 7.GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip peripheral functions such as ...
Page 51
Direct LED Drive The Port C pins provide a current sinked output capable of driving an LED without requir- ing an external resistor. The output sinks current at programmable levels of 3mA, 7mA, 13mA and 20mA. This mode is enabled ...
Page 52
In the 20- and 28-pin versions of this device, any pin which shares functionality with an Note: ADC, crystal or comparator port is not 5V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5V-tolerant, and can safely handle ...
Page 53
Table 15. Port Alternate Function Mapping (Continued)(Non 8-Pin Parts) Port Pin Mnemonic PB0 Reserved Port B ANA0 PB1 Reserved ANA1 PB2 Reserved ANA2 PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF PB6 Reserved Reserved PB7 Reserved Reserved Note: Because ...
Page 54
Table 15. Port Alternate Function Mapping (Continued)(Non 8-Pin Parts) Port Pin Mnemonic PC0 Reserved Port C ANA4/CINP/LED Drive PC1 Reserved ANA5/CINN/ LED Drive PC2 Reserved ANA6/LED PC3 COUT LED PC4 Reserved LED PC5 Reserved LED PC6 Reserved LED PC7 Reserved ...
Page 55
Table 16. Port Alternate Function Mapping (8-Pin Parts) Port Pin Mnemonic PA0 T0IN Port A Reserved Reserved T0OUT PA1 T0OUT Reserved CLKIN Analog Functions* ADC Analog Input/VREF PA2 DE0 RESET T1OUT Reserved PA3 CTS0 COUT T1IN Analog Functions* ADC Analog ...
Page 56
GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con- figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other ...
Page 57
Port A–C Address Registers The Port A–C Address registers select the GPIO Port functionality accessible through the Port A–C Control registers. The Port A–C Address and Control registers combine to pro- vide access to all GPIO Port controls (Table 18). ...
Page 58
Table 19. Port A–C Control Registers (PxCTL) BITS 7 6 FIELD RESET R/W R/W R/W ADDR PCTL[7:0]—Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation. Port A–C Data Direction Sub-Registers The Port ...
Page 59
Caution: Do not enable alternate functions for GPIO port pins for which there is no associated alternate function. Failure to follow this guideline can result in unpredictable operation. Table 21. Port A–C Alternate Function Sub-Registers (PxAF) BITS 7 6 AF7 ...
Page 60
Port A–C High Drive Enable Sub-Registers The Port A–C High Drive Enable sub-register (Table 23) is accessed through the Port A–C Control register by writing the Port A–C High Drive Enable sub-registers to 1 configures the specified port pins for ...
Page 61
Port A–C Pull-up Enable Sub-Registers The Port A–C Pull-up Enable sub-register (Table 25) is accessed through the Port A–C Control register by writing Port A–C Pull-up Enable sub-registers enables a weak internal resistive pull-up on the specified Port pins. Table ...
Page 62
Port A–C Alternate Function Set 2 Sub-Registers The Port A–C Alternate Function Set 2 sub-register (Table 27) is accessed through the Port A–C Control register by writing Function Set 2 sub-registers selects the alternate function available at a port pin. ...
Page 63
Input data is logical 0 (Low Input data is logical 1 (High). Port A–C Output Data Register The Port A–C Output Data register (Table 29) controls the output data to the pins. Table 29. Port A–C ...
Page 64
LED Drive Level High Register The LED Drive Level registers contain two control bits for each Port C pin (Table 31). These two bits select between four programmable drive levels. Each pin is individually programmable. Table 31. LED Drive Level ...
Page 65
... Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man- ual is available for download at www.zilog.com. Interrupt Vector Listing Table 33 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address ...
Page 66
Table 33. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watch-Dog Timer (see Watch-Dog Timer chapter) 003AH Primary Oscillator Fail Trap (not an interrupt) ...
Page 67
Table 33. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source Lowest 0036H Port C0, both input edges 0038H Reserved Architecture Figure 8 illustrates the interrupt controller block diagram. Port Interrupts ...
Page 68
Writing the IRQE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions: • Execution (Disable Interrupt) instruction • eZ8 CPU acknowledgement of an interrupt service request ...
Page 69
To avoid missing interrupts, use the following coding style to clear bits in Caution: the Interrupt Request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code can generate interrupts directly. Writing ...
Page 70
Table 34. Interrupt Request 0 Register (IRQ0) BITS 7 6 Reserved T1I FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. T1I—Timer 1 Interrupt Request interrupt request is pending for Timer ...
Page 71
Table 35. Interrupt Request 1 Register (IRQ1) BITS 7 6 PA7VI PA6CI FIELD 0 0 RESET R/W R/W R/W ADDR PA7VI—Port A7 Interrupt Request interrupt request is pending for GPIO Port interrupt request ...
Page 72
IRQ0 Enable High and Low Bit Registers Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg- isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt Request 0 ...
Page 73
T1ENL—Timer 1 Interrupt Request Enable Low Bit T0ENL—Timer 0 Interrupt Request Enable Low Bit U0RENL—UART 0 Receive Interrupt Request Enable Low Bit U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit ADCENL—ADC Interrupt Request Enable Low Bit IRQ1 Enable High and ...
Page 74
Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL) BITS 7 6 PA7VENL PA6CENL FIELD 0 0 RESET R/W R/W R/W ADDR PA7VENH—Port A Bit[7] Interrupt Request Enable Low Bit PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit PAxENL—Port ...
Page 75
C1ENH—Port C1 Interrupt Request Enable High Bit C0ENH—Port C0 Interrupt Request Enable High Bit Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL) BITS 7 6 Reserved FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. C3ENL—Port C3 Interrupt ...
Page 76
Because these shared interrupts are edge-triggered possible to generate an interrupt just by switching from one shared source to another. For this reason, an interrupt must be disabled before switching between sources. Table 47. Shared Interrupt Select Register ...
Page 77
Timers Overview These Z8 Encore! that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The timers’ features include: • 16-bit reload counter • Programmable prescaler with prescale values from 1 to 128 • PWM ...
Page 78
Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale ...
Page 79
Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT mode. ...
Page 80
If using the Timer Output alternate function, set the initial output level (High or – Low). 2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This action only affects the first ...
Page 81
Select either the rising edge or falling edge of the Timer Input signal for the count. – This selection also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is ...
Page 82
Select either the rising edge or falling edge of the comparator output signal for the – count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is not ...
Page 83
Write to the Timer Control register to: Disable the timer – Configure the timer for PWM mode. – Set the prescale value. – Set the initial logic level (High or Low) and PWM High/Low transition for the – Timer ...
Page 84
Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and ...
Page 85
If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin for the Timer Output and Timer Output Complement alternate functions. The Timer Output ...
Page 86
Write to the Timer Control register to: Disable the timer – Configure the timer for CAPTURE mode. – Set the prescale value. – Set the Capture edge (rising or falling) for the Timer Input. – 2. Write to the ...
Page 87
The steps for configuring a timer for CAPTURE RESTART mode and initiating the count are as follows: 1. Write to the Timer Control register to: Disable the timer – Configure the timer for CAPTURE RESTART mode. Setting the mode also ...
Page 88
Write to the Timer Control register to: Disable the timer – Configure the timer for Compare mode. – Set the prescale value. – Set the initial logic level (High or Low) for the Timer Output alternate function, if – ...
Page 89
Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the ...
Page 90
Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to ...
Page 91
Timer Control Register Definitions Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers (Tables 49 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read ...
Page 92
Reload value. In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit Compare value. Table 51. Timer 0–1 Reload High Byte Register (TxRH) BITS 7 6 FIELD 1 1 RESET R/W R/W R/W ADDR Table 52. ...
Page 93
Table 54. Timer 0–1 PWM Low Byte Register (TxPWML) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR PWMH and PWML—Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared ...
Page 94
Timer Interrupt occurs on all defined Reload, Compare and Input Events 10 = Timer Interrupt only on defined Input Capture/Deassertion Events 11 = Timer Interrupt only on defined Reload/Compare Events Reserved—Must be 0. PWMD—PWM Delay value This field ...
Page 95
When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer ...
Page 96
Timer Output and the Timer Output Complement is forced to High (1 Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. ...
Page 97
PWM Single Output mode 0100 = Capture mode 0101 = Compare mode 0110 = Gated mode 0111 = Capture/Compare mode 1000 = PWM Dual Output mode 1001 = Capture Restart mode 1010 = Comparator Counter Mode PS025203-0405 Z8 ...
Page 98
Watch-Dog Timer Overview The Watch-Dog Timer (WDT) protects against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore! devices into unsuitable operating states. The Watch-Dog Timer includes the following fea- tures: • On-chip ...
Page 99
Table 57. Watch-Dog Timer Approximate Time-Out Delays WDT Reload Value WDT Reload Value (Hex) (Decimal) 000004 FFFFFF 16,777,215 Watch-Dog Timer Refresh When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog ...
Page 100
WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! Z8F0823 Series are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request. Both ...
Page 101
All three Watch-Dog Timer Reload registers must be written in the order just listed. There must be no other register writes between each of these operations register write occurs, the lock state machine resets and no further writes ...
Page 102
The 24-bit WDT Reload Value must not be set to a value less than Caution: Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD 1 1 RESET R/W* R/W* R/W ADDR R/W* - Read returns the ...
Page 103
UART Overview The Universal Asynchronous Receiver/Transmitter (UART full-duplex communica- tion channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: • 8-bit asynchronous data transfer ...
Page 104
Parity Checker RXD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TXD Register Parity Generator CTS DE Operation Data Format The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An ...
Page 105
Idle State of Line lsb 1 Start Bit0 0 Figure 11.UART Asynchronous Data Format without Parity Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 12.UART Asynchronous Data Format with Parity Transmitting Data using the Polled Method Follow ...
Page 106
Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a ...
Page 107
The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write ...
Page 108
Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error condi- tions). Follow these steps to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate ...
Page 109
Executes the IRET instruction to return from the interrupt-service routine and await more data. Clear To Send (CTS) Operation The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control on the ...
Page 110
The following three MULTIPROCESSOR modes are available in hardware: • Interrupt on all address bytes • Interrupt on matched address bytes and correctly framed data bytes • Interrupt only on correctly framed data bytes These ...
Page 111
UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after ...
Page 112
Receiver Interrupts The receiver generates an interrupt when any of the following occurs: • A data byte is received and is available in the UART Receive Data register. This interrupt can be disabled independently of the other receiver interrupt sources. ...
Page 113
Read Data Figure 15.UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the Baud ...
Page 114
UART. The UART data rate is calculated using the following equation: UART Data Rate (bits/s) When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit ...
Page 115
TXD—Transmit Data UART transmitter data byte to be shifted out through the TXDx pin. UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data register (Table 63). The read-only UART Receive Data ...
Page 116
No parity error has occurred parity error has occurred. OE—Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has ...
Page 117
Table 65. UART Status 1 Register (U0STAT1 R/W ADDR Reserved—Must be 0. NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit The current byte is ...
Page 118
PEN—Parity Enable This bit enables or disables parity. Even or odd is determined by the PSEL bit Parity is disabled The transmitter sends data with an additional parity bit and the receiver receives an additional parity ...
Page 119
MPBT—Multiprocessor Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit is used by the receiving device to determine if the data byte contains address or data infor- mation Send a 0 ...
Page 120
Table 68. UART Address Compare Register (U0ADDR) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR COMP_ADDR—Compare Address This 8-bit value is compared to incoming address bytes. UART Baud Rate High and Low Byte Registers The UART Baud ...
Page 121
UART Baud Rate Divisor Value (BRG) The baud rate error relative to the acceptable baud rate is calculated using the following equation: UART Baud Rate Error (%) For reliable communication, the UART baud rate error must never exceed 5 percent. ...
Page 122
Infrared Encoder/Decoder Overview ® The Z8 Encore! UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on- chip UART to allow easy communication between the Z8 Encore! and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared ...
Page 123
Infrared Endec through the RXD pin, decoded by the Infrared Endec, and passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the ...
Page 124
Receiving IrDA Data Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to ...
Page 125
If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 ...
Page 126
Analog-to-Digital Converter Overview The Analog-to-Digital Converter (ADC) converts an analog input signal to its digital rep- resentation. The features of this sigma-delta ADC include: • 10-bit resolution • 8 single-ended analog input sources are multiplexed with general-purpose I/O ports • ...
Page 127
Internal Voltage Vrefsel Reference Generator Ref Input 11 ADC Data Analog Input ADC IRQ Figure 19.Analog-to-Digital Converter Block Diagram Operation Data Format The output of the ADC is an 11- bit, signed, two’s complement digital value. The output generally ...
Page 128
As a result, the final value is an 11- bit number. Automatic Powerdown If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of ...
Page 129
ADCD_L[7:5]}. – CEN resets indicate the conversion is complete. – the ADC remains idle for 160 consecutive system clock cycles automatically powered-down. Continuous Conversion When configured for ...
Page 130
... Devices that have been factory calibrated contain 9 bytes of calibration data in the Flash option bit space. This data consists of 3 bytes for each reference type. See “ZiLOG Cali- bration Bits” on page 137 for a list of input modes for which calibration data exists. There is 1 byte for offset, 2 bytes for gain correction ...
Page 131
GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and ADC is the uncompensated value read from the ADC. The OFFCAL value is in uncomp two’s complement format, as are the compensated and uncompensated ADC values. ...
Page 132
REFEXT External Reference Select - 0 = External reference buffer is disabled; Vref pin is available for GPIO functions 1 = The internal ADC reference is buffered and connected to the Vref pin CONT 0 = Single-shot conversion. ADC data ...
Page 133
ADC Control/Status Register 1 The second ADC Control register contains the voltage reference level selection bit. Table 73. ADC Control/Status Register 1 (ADCCTL1 BITS REFSELH FIELD 1 0 RESET R/W R/W R/W ADDR REFSELH—Voltage Reference Level Select High ...
Page 134
ADC Data Low Bits Register The ADC Data Low Byte register contains the lower bits of the ADC output as well as an overflow status bit. The output is a 11-bit two’s complement value. During a single-shot conversion, this value ...
Page 135
Comparator Overview ® The Z8 Encore! pares two analog input signals. A GPIO ( input. The negative input ( internal reference. The output is available as an interrupt source or can be routed to an external pin using the GPIO ...
Page 136
Comparator Control Register Definitions Comparator Control Register The Comparator Control Register (CMPCTL) configures the comparator inputs and sets the value of the internal voltage reference. Table 76. Comparator Control Register (CMP0) BITS 7 6 INPSEL INNSEL FIELD 0 0 RESET ...
Page 137
Flash Memory Overview The products in the Z8 Encore! tile Flash memory with read/write/erase capability. The Flash Memory can be pro- grammed and erased in-circuit by either user code or through the On-Chip Debugger. The Flash memory array is arranged ...
Page 138
Sectors 1024 Bytes each Figure 20.Flash Memory Arrangement Flash Information Area The Flash information area is separate from program memory and is mapped to the address range FE00H values for the analog peripherals are stored here. Factory calibration data ...
Page 139
Operation The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for byte programming, Page Erase, and Mass Erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental ...
Page 140
Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...
Page 141
Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasing ...
Page 142
Table 78. Flash Code Protection Using the Flash Option Bits FHSWP FWP Flash Code Protection Using the Flash Controller At Reset, the Flash Controller locks to prevent accidental program or erasure of the ...
Page 143
... With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the value to the Flash Control register initiates the Mass Erase operation. While the Flash 63H PS025203-0405 Z8 Encore! FFH )for a description of the LDC and www.zilog.com . The Flash Page Select register identi- FFH ® Z8F0823 Series Product Specification 126 ) ...
Page 144
... Please refer to the document entitled Third-Party Flash Programming Support for Z8 ® Encore! for more information about bypassing the Flash Controller. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: • ...
Page 145
Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control register before program- ming or erasing the Flash memory. Writing the sequence Flash Control register unlocks the Flash Controller. When the Flash Controller ...
Page 146
Table 80. Flash Status Register (FSTAT R/W ADDR Reserved—Must be 0. FSTAT—Flash Controller Status 000000 = Flash Controller locked. 000001 = First unlock command received (73H written). 000010 = Second unlock command received (8CH written). 000011 = Flash ...
Page 147
Program Memory Address[15:9] = PAGE[6:0]. For the Z8F0823 devices, the upper 3 bits must always be 0. Flash Sector Protect Register The Flash Sector Protect register is shared with the Flash Page Select Register. When the Flash Control Register address ...
Page 148
Table 83. Flash Frequency High Byte Register (FFREQH) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR FFREQH—Flash Frequency High Byte High byte of the 16-bit Flash Frequency value. Table 84. Flash Frequency Low Byte Register (FFREQL) BITS ...
Page 149
Flash Option Bits Overview Programmable Flash Option Bits allow user configuration of certain aspects of Z8 ® Encore! Z8F0823 Series operation. The feature configuration data is stored in the Flash Program Memory and read during Reset. The features available for ...
Page 150
Option Bit Types User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits has been provided because these locations contain application-specific device configurations. The information contained here is ...
Page 151
Flash Option Bit Control Register Definitions Trim Bit Address Register This register contains the target address for an access to the trim option bits. Table 85. Trim Bit Address Register (TRMADR) BITS 7 6 FIELD 0 0 RESET R/W R/W ...
Page 152
Flash Program Memory Address 0000H Table 87. Flash Option Bits at Program Memory Address 0000H BITS 7 6 WDT_RES WDT_AO FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. WDT_RES—Watch-Dog Timer Reset ...
Page 153
Flash Program Memory Address 0001H Table 88. Flash Options Bits at Program Memory Address 0001H BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. Reserved—Must be 1. Trim Bit ...
Page 154
... Trim Bit Address 0004H—Reserved ZiLOG Calibration Bits ADC Calibration Bits Table 90. ADC Calibration Bits at 0060H-007DH BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. ADC_CAL—Analog to Digital Converter Calibration Values Contains factory calibrated values for ADC gain and offset compensation. Each of the three supported reference types has one byte of offset calibration and two bytes of gain calibration ...
Page 155
On-Chip Debugger Overview ® The Z8 Encore! (OCD) that provides advanced debugging features including: • Reading and writing of the Register File • Reading and writing of Program and Data Memory • Setting of Breakpoints and Watchpoints • Executing eZ8 ...
Page 156
Operation OCD Interface The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur ...
Page 157
RS-232 TX RS-232 RX Figure 24.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: • The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless ...
Page 158
Asserting the RESET pin Low to initiate a Reset. • Driving the DBG pin Low while the device is in STOP mode initiates a System Reset. OCD Data Format The OCD interface uses the asynchronous data format defined for ...
Page 159
OCD Serial Errors The On-Chip Debugger can detect any of the following error conditions on the DBG pin: • Serial Break (a minimum of nine continuous bits Low) • Framing Error (received • Transmit Collision (OCD and host simultaneous transmission ...
Page 160
On-Chip Debugger Commands The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are avail- able. In DEBUG mode, all OCD commands become available unless ...
Page 161
Command Debug Command Execute Instruction Reserved 13H–FFH In the following bulleted list of OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by ’ On-Chip Debugger back to the host is identified by ’ ...
Page 162
Write Program Counter (06H)—The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the ...
Page 163
DBG 0AH ← DBG Program Memory Address[15:8] ← DBG Program Memory Address[7:0] ← DBG Size[15:8] ← DBG Size[7:0] ← DBG 1-65536 data bytes • Read Program Memory (0BH)—The Read Program Memory command reads data from Program Memory. This command ...
Page 164
FFFFH from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately ...
Page 165
Table 93. OCD Control Register (OCDCTL) BITS 7 6 DBGMODE BRKEN FIELD 0 0 RESET R/W R/W R/W DBGMODE—Debug Mode The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU stops fetching ...
Page 166
Table 94. OCD Status Register (OCDSTAT) BITS 7 6 DBG HALT FIELD 0 0 RESET R R R/W DBG—Debug Status 0 = NORMAL mode 1 = DEBUG mode HALT—HALT Mode 0 = Not in HALT mode HALT ...
Page 167
Oscillator Control Overview ® The Z8 Encore! user-selectable: • On-chip precision trimmed RC oscillator • External clock drive • On-chip low precision Watch-Dog Timer oscillator In addition, Z8 Encore! recovery circuitry, allowing continued operation despite a failure of the primary ...
Page 168
Table 95. Oscillator Configuration and Selection (Continued) Clock Source Characteristics External Clock • 20MHz Drive • Accuracy dependent on external clock source Internal Watchdog • 10KHz nominal Timer Oscillator • ± 40% accuracy; no external components required • ...
Page 169
Although this oscillator runs at a much slower speed than the original system clock, the CPU continues to operate, allowing execution of a clock failure vector and software rou- tines that either remedy the oscillator failure or issue a failure ...
Page 170
Table 96. Oscillator Control Register (OSCCTL) BITS 7 6 INTEN Reserved FIELD 1 0 RESET R/W R/W R/W ADDR INTEN—Internal Precision Oscillator Enable 1 = Internal precision oscillator is enabled 0 = Internal precision oscillator is disabled Reserved—Must be 0 ...
Page 171
Internal Precision Oscillator Overview The Internal Precision Oscillator (IPO) is designed for use without external components. The user can either manually trim the oscillator for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53MHz frequency. IPO ...
Page 172
CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a ...
Page 173
Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ’source, destination’, but ordering is opcode-dependent. The ...
Page 174
Notation Description b Bit cc Condition Code DA Direct Address ER Extended Addressing Register IM Immediate Data Ir Indirect Working Register IR Indirect Register Irr Indirect Working Register Pair IRR Indirect Register Pair p Polarity r Working Register R ...
Page 175
Assignment of a value is indicated by an arrow. For example, ← dst dst + src indicates the source data is added to the destination data and the result is stored in the des- tination location. eZ8 CPU Instruction Classes ...
Page 176
Tables 101 through 108 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than ...
Page 177
Table 102. Bit Manipulation Instructions Mnemonic Operands BCLR bit, dst BIT p, bit, dst BSET bit, dst BSWAP dst CCF — RCF — SCF — TCM dst, src TCMX dst, src TM dst, src TMX dst, src Table 103. Block ...
Page 178
Mnemonic STOP WDT Mnemonic Operands Instruction CLR dst LD dst, src LDC dst, src LDCI dst, src LDE dst, src LDEI dst, src LDWX dst, src LDX dst, src LEA dst, X(src) Load Effective Address POP dst POPX dst PUSH ...
Page 179
Mnemonic Operands Instruction XOR dst, src XORX dst, src Table 107. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET RET TRAP Table 108. Rotate and Shift Instructions Mnemonic BSWAP RL RLC ...
Page 180
Table 108. Rotate and Shift Instructions Mnemonic SRL SWAP eZ8 CPU Instruction Summary Table 109 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU ...
Page 181
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst AND src AND dst, src dst ← dst AND src ANDX dst, src ATM Block all interrupt and DMA requests during execution of the next 3 ...
Page 182
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← ~dst COM dst CP dst, src dst - src CPC dst, src dst - src - C CPCX dst, src dst - src - C CPX dst, ...
Page 183
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation HALT Halt Mode dst ← dst + 1 INC dst dst ← dst + 1 INCW dst FLAGS ← @SP IRET SP ← ← @SP ...
Page 184
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← src LDC dst, src dst ← src LDCI dst, src r ← ← dst ← src LDE dst, src dst ...
Page 185
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst OR src OR dst, src dst ← dst OR src ORX dst, src dst ← @SP POP dst SP ← dst ← @SP ...
Page 186
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation RR dst dst RRC dst dst dst ← dst – src - C ...
Page 187
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst – src SUBX dst, src dst[7:4] ↔ dst[3:0] SWAP dst TCM dst, src (NOT dst) AND src TCMX dst, src (NOT dst) AND src TM dst, ...
Page 188
Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst XOR src XOR dst, src dst ← dst XOR src XORX dst, src Flags Notation Value is a function of the result of the ...
Page 189
Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 26. Figures 27 and 32 provide information about each of the eZ8 CPU instructions. Table 110 lists Opcode Map abbreviations. Opcode Upper Nibble First ...
Page 190
Table 110. Opcode Map Abbreviations Abbreviation Description b Bit position cc Condition code X 8-bit signed index or displacement DA Destination address ER Extended Addressing register IM Immediate data value Ir Indirect Working Register IR Indirect register Irr Indirect Working ...
Page 191
BRK SRP ADD ADD 0 IM r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 RLC RLC ADC ADC 1 R1 IR1 r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 INC INC SUB SUB 2 R1 IR1 ...
Page 192
PUSH 3.3 3.4 CPC CPC A r1,r2 r1,Ir2 B 3.2 3.3 SRL SRL C R1 IR1 Figure 28.Second Opcode Map ...
Page 193
Electrical Characteristics The data in this chapter is pre-qualification and pre-characterization and is subject to change. Additional electrical characteristics may be found in the individual chapters. Absolute Maximum Ratings Stresses greater than those listed in Table 111 may cause permanent ...
Page 194
DC Characteristics Table 112 lists the DC characteristics of the Z8 Encore! voltages are referenced to V Symbol Parameter V Supply Voltage DD V Low Level Input Voltage IL1 V Low Level Input Voltage IL2 V High Level Input Voltage ...
Page 195
Table 112. DC Characteristics (Continued) Symbol Parameter ICCH Supply Current in Halt Mode ICCS Supply Current in STOP Mode 1 This condition excludes all pins that have on-chip pull-ups, when driven Low. 2 These values are provided for design guidance ...
Page 196
AC Characteristics The section provides information about the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs. Symbol Parameter F System Clock Frequency SYSCLK F Internal Precision Oscillator IPO Frequency F Internal ...
Page 197
On-Chip Peripheral AC and DC Electrical Characteristics Table 114. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing Symbol Parameter V Power-On Reset Voltage POR Threshold V Voltage Brown-Out VBO Reset Voltage Threshold hysteresis POR VBO Starting ...
Page 198
Table 115. Flash Memory Electrical Characteristics and Timing Parameter Minimum Flash Mass Erase Time Writes to Single Address Before Next Erase Flash Row Program Time Data Retention Endurance 10,000 Table 116. Watch-Dog Timer Electrical Characteristics and Timing Symbol Parameter F ...
Page 199
Table 117. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued) Symbol Parameter Offset Error (single-ended) V Internal Reference Voltage REF Single-Shot Conversion Time Continuous Conversion Time Sampling Rate Signal Input Bandwidth R Analog Source Impedance S Zin Input Impedance Vin Input ...
Page 200
General Purpose I/O Port Input Data Sample Timing Figure 30 illustrates timing of the GPIO Port input sampling. The input value on a GPIO Port pin is sampled on the rising edge of the system clock. The Port value is ...