STM8S103K3T6C STMicroelectronics, STM8S103K3T6C Datasheet - Page 17

• Manufacturer Part Number: STM8S103K3T6C
• Description: MCU 8KB FLASH MEM 16MHZ 32-LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S103K3T6C

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: STM8S10x
• Core: STM8
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Development Tools By Supplier: STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
• For Use With: 497-10593 - KIT STARTER FOR STM8S207/8 SER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8945; STM8S103K3T6C

STM8S103K3 STM8S103F3 STM8S103F2
4.14
4.14.1
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Communication interfaces
The following communication interfaces are implemented:
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UART1
Main features
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Asynchronous communication (UART mode)
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Synchronous communication
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Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
SPI : Full and half-duplex, 8 Mbit/s
I²C: Up to 400 Kbit/s
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
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Transmission error detection with interrupt generation
Parity control
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
Address bit (MSB)
Idle line (interrupt)
DocID15441 Rev 6
CPU
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CPU
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