ST62T62CM3 STMicroelectronics, ST62T62CM3 Datasheet - Page 30

• Manufacturer Part Number: ST62T62CM3
• Description: IC MCU 8BIT W/ADC 16-SOIC
• Manufacturer: STMicroelectronics
• Series: ST6r

Specifications of ST62T62CM3

• Core Processor: ST6
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 9
• Program Memory Size: 1.8KB (1.8K x 8)
• Program Memory Type: OTP
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: ST62T6x
• Core: ST6
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 9
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST6252C ST6262B ST6262C
INTERRUPTS (Cont’d)
3.5.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
30/75
GENERAL
TIMER
A/D CONVERTER
AR TIMER
Port PAn
Port PBn
Port PCn
7
-
Peripheral
LES
ESB
IOR
TSCR1
ADCR
ARMC
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
GEN
Register
-
-
C8h
D4h
D1h
D5h
C0h-C4h
C1h-C5h
C2h-C6h
Address
Register
-
0
-
GEN
ETI
EAI
OVIE
CPIE
EIE
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
Mask bit
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.5.4 Interrupt Sources
Interrupt
ST62E62C/T62C are summarized in the
with associated mask bit to enable/disable the in-
terrupt request.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
PAn pin
PBn pin
PCn pin
sources
Masked Interrupt Source
available
I
on
Vector 4
Vector 4
Vector 3
Vector 1
Vector 1
Vector 2
Interrupt
Table 10
vector
the