STM32F101C8U6 STMicroelectronics, STM32F101C8U6 Datasheet - Page 83

• Manufacturer Part Number: STM32F101C8U6
• Description: MCU 32BIT ARM 128K FLASH 48-QFN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101C8U6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP Exposed Pad, 48-eLQFP, 48-HLQFP
• Processor Series: STM32F101x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 10 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• Featured Product: STM32 Cortex-M3 Companion Products
• Eeprom Size: -
• For Use With: 497-10030 - STARTER KIT FOR STM32497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F101x8, STM32F101xB
Table 54.
22-May-2008
14-Mar-2008
21-Mar-2008
Date
Document revision history (continued)
Revision
5
6
7
Figure 2: Clock tree on page 13
CRC added (see
page 9
Maximum T
P
in
I
Stop and Standby modes on page
ACC
note 2 removed.
t
V
page
Table 41: SPI characteristics on page 63
I
Table 44: ADC accuracy - limited test conditions
Section 6.2: Thermal characteristics on page 77
Appendix A: Important notes
Small text changes.
In
– N
– cycling conditions specified for t
– t
Figure 2: Clock tree
V
CRC feature removed.
Section 1: Introduction
throughout the family
I
mode on page
Values added to
V) on page
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 64
modified.
Section 6.2.2: Evaluating the maximum junction temperature for an
application on page 78
Axx option added to
accuracy
LQFP100 package specifications updated (see
characteristics on page
Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints
added (see
DD
RET
VREF
DD_VBAT
D
NF(NRST)
25
Table 27: Flash memory characteristics on page
Table 28: Flash memory endurance and data
, T
RET
, Avg_Slope and T
END
modified in
HSI
Doc ID 13586 Rev 14
modified in
A
59.
added in
and T
min modified at T
and
tested over the whole temperature range
modified in
removed from
modified.
Equation 1
unit corrected in
62.
J
Figure 8: Memory map on page 28
Figure
J
value given in
added, t
42.
Table 15: Typical and maximum current consumptions in
Table 42: ADC characteristics on page
Table 28: Flash memory endurance and data
Table 40: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3
CRC (cyclic redundancy check) calculation unit on
42,
Table 23: HSI oscillator characteristics on page
corrected.
Table 53: Ordering information scheme on page
corrected.
added. CRC feature added.
L
prog
Figure
modified,
Table 21: Typical current consumption in Standby
added.
modified in
71).
A
= 55 °C
values modified and t
Table 37: NRST pin characteristics on
Table 7: Thermal characteristics on page
removed.
44,
Figure 8: Memory map
Changes
added.
Section 2.2: Full compatibility
Figure 46
RET
38.
Table 46: TS
modified.
and
for address).
Section 6: Package
prog
retention:
Figure
added.
characteristics.
modified.
50.
description clarified
Revision history
66.
clarified.
40).
Table 45: ADC
retention.
48,
83/87
32.
79.