STM32F101C8U6 STMicroelectronics, STM32F101C8U6 Datasheet - Page 84

• Manufacturer Part Number: STM32F101C8U6
• Description: MCU 32BIT ARM 128K FLASH 48-QFN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101C8U6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP Exposed Pad, 48-eLQFP, 48-HLQFP
• Processor Series: STM32F101x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 10 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• Featured Product: STM32 Cortex-M3 Companion Products
• Eeprom Size: -
• For Use With: 497-10030 - STARTER KIT FOR STM32497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Revision history
84/87
Table 54.
23-Sep-2008
21-Jul-2008
24-Jul-2008
Date
Document revision history (continued)
Revision
10
8
9
Small text changes.
Power supply supervisor on page 16
Table 8: General operating conditions on page
Capacitance modified in
Table notes revised in
Maximum value of t
power control block characteristics on page
Values added to
in Stop and Standby modes
Standby mode
f
characteristics on page
characteristics on page
f
Minimum SDA and SCL fall time value for Fast mode removed from
Table 39: I2C characteristics on page
t
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page
C
Figure 34: Typical connection diagram using the ADC
f
Table 45: ADC
Typical T
page
LQFP48 package specifications updated (see
Table
Axx option removed from
page
First page modified: “Up to 2 x I²C interfaces” instead of “1 x I²C
interface”
STM32F101xx devices with 32 Kbyte Flash memory capacity removed,
document updated accordingly.
Section 2.2: Full compatibility throughout the family on page 14
Notes modified in
on page
Note 2
|ΔV
Note 2
Measurement conditions specified in
characteristics on page
I
current consumptions in Stop and Standby modes on page
General input/output characteristics on page 54
Note added below
Section 7.1: Future family enhancements
HSE_ext
HCLK
h(NSS)
PCLK2
DD
ADC
DDx
in standby mode at 85 °C modified in
Doc ID 13586 Rev 14
70.
79.
corrected in
modified in
46).
| min and |ΔV
corrected in
modified in
modified below
added to
modified in
24.
S_temp
removed.
accuracy.
value removed from
Table 8: General operating conditions on page
Table 15: Typical and maximum current consumptions
Table 42: ADC characteristics on page 66
Table 4: Medium-density STM32F101xx pin definitions
Table 29: EMS
Table 41: SPI characteristics on page 63
Table 53: Ordering information
RSTTEMPO
Table 44: ADC accuracy - limited test conditions
Table 19: High-speed external user clock
DDx
Section 5: Electrical
Table 5: Voltage characteristics on page
| min removed.
44. f
49.
35.
Figure 11: Power supply scheme on page
Table 53: Ordering information scheme on
and
PLL_IN
modified in
Changes
Table 21: Typical current consumption in
characteristics.
modified in
Table 46: TS characteristics on
modified and V
Section 5.3.5: Supply current
61, note 1 modified.
STM32F101x8, STM32F101xB
Table 15: Typical and maximum
Table 10: Embedded reset and
removed. Small text changes.
characteristics.
34.
Table
Table 26: PLL
32.
modified.
scheme.
DDA
51,
modified.
Table 45
added to
38.
and
and
updated.
31,
32.
and
30.
and
64.