STM32F101RCT6TR STMicroelectronics, STM32F101RCT6TR Datasheet - Page 92

• Manufacturer Part Number: STM32F101RCT6TR
• Description: MCU 32BIT ARM 64K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101RCT6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: STM32F101x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 9
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STM3210E-EVAL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• For Use With: 497-10030 - STARTER KIT FOR STM32497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Table 57.
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Guaranteed by characterization, not tested in production.
92/106
I
I
DNL
INL
Offset
Gain error
t
Update rate
t
PSRR+
DDVREF+
DDA
SETTLING
WAKEUP
Symbol
(3)
(3)
(3)
(2)
(3)
(3)
(3)
(3)
DAC characteristics (continued)
DAC DC current consumption
in quiescent mode (Standby
mode)
DAC DC current consumption
in quiescent mode (Standby
mode)
Differential non linearity
Difference between two
consecutive code-1LSB)
Integral non linearity (difference
between measured value at
Code i and the value at Code i
on a line drawn between Code
0 and last Code 1023)
Offset error
(difference between measured
value at Code (0x800) and the
ideal value = V
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final value
±1LSB
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from
code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the DAC
Control register)
Power supply rejection ratio (to
V
DDA
) (static DC measurement
Parameter
REF+
/2)
Doc ID 14610 Rev 7
Min
3
6.5
–67
Typ
STM32F101xC, STM32F101xD, STM32F101xE
220
380
480
±0.5
±2
±1
±4
±10
±3
±12
±0.5
4
1
10
–40
Max
(1)
µA
µA
µA
LSB
LSB
LSB
LSB
mV
LSB
LSB
%
µs
MS/s C
µs
dB
Unit
With no load, worst code
(0xF1C) at V
terms of DC consumption on
the inputs.
With no load, middle code
(0x800) on the inputs.
With no load, worst code
(0xF1C) at V
terms of DC consumption on
the inputs.
Given for the DAC in 10-bit
configuration.
Given for the DAC in 12-bit
configuration.
Given for the DAC in 10-bit
configuration.
Given for the DAC in 12-bit
configuration.
Given for the DAC in 12-bit
configuration.
Given for the DAC in 10-bit at
V
Given for the DAC in 12-bit at
V
Given for the DAC in 12bit
configuration.
C
C
input code between lowest and
highest possible ones.
No R
REF+
REF+
LOAD
LOAD
LOAD
LOAD
= 3.6 V.
= 3.6 V.
 50 pF, R
 50 pF, R
 50 pF, R
Comments
, C
REF+
REF+
LOAD
LOAD
LOAD
LOAD
= 3.6 V in
= 3.6 V in
= 50 pF
 5 k
 5 k
 5 k