ST62T65CM6 STMicroelectronics, ST62T65CM6 Datasheet - Page 50

IC MCU 8BIT OTP/EPROM 28 PSOIC

ST62T65CM6

Manufacturer Part Number
ST62T65CM6
Description
IC MCU 8BIT OTP/EPROM 28 PSOIC
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T65CM6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LED, LVD, POR, WDT
Number Of I /o
21
Program Memory Size
3.8KB (3.8K x 8)
Program Memory Type
OTP
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST6
No. Of I/o's
21
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2103-5

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ST6255C ST6265C ST6265B
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: D7h — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 14. Prescaler Division Ratio Selection
Bit 4 = D4: Reserved. Must be kept reset.
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
15:
Table 15. Clock Source Selection.
50/84
PS2
PS2
7
0
0
0
0
1
1
1
1
CC1
SL1
X
0
1
0
0
1
1
PS1
PS1
0
0
1
1
0
0
1
1
PS0
CC0
SL0
0
1
1
0
1
0
1
PS0
0
1
0
1
0
1
0
1
D4
F
F
ARTIMin Input Clock
Reserved
Disabled
Rising Edge
Falling Edge
int
int
Divided by 3
SL1
ARPSC Division Ratio
Edge Detection
Clock Source
SL0
128
16
32
64
1
2
4
8
CC1
Table
CC0
0
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: DBh — Read/Write
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: D9h — Read/Write
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: DAh — Read/Write
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bits.
D7
D7
D7
7
7
7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
0
0
0

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