ST72C334J4T6 STMicroelectronics, ST72C334J4T6 Datasheet

MCU 8BIT FLASH SPI SCI 44TQFP

ST72C334J4T6

Manufacturer Part Number
ST72C334J4T6
Description
MCU 8BIT FLASH SPI SCI 44TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72C334J4T6

Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72C3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7C334-INDART, ST7MDT2-EPB2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4838

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Part Number:
ST72C334J4T6
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Quantity:
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ST72C334J4T6
Manufacturer:
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Manufacturer:
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Device Summary
April 2003
Program memory - bytes
RAM (stack) - bytes
EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
– 8K or 16K Program memory (ROM or single
– 256 bytes EEPROM Data memory (with read-
– 384 or 512 bytes RAM
– Enhanced reset system
– Enhanced low voltage supply supervisor with
– Clock sources: crystal/ceramic resonator os-
– 4 Power Saving Modes: Halt, Active-Halt,
– Beep and clock-out capabilities
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
– 44 or 32 multifunctional bidirectional I/O lines:
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
– Configurable watchdog timer
– Realtime base
– Two 16-bit timers with: 2 input captures (only
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN com-
Memories
Clock, Reset and Supply Management
Interrupt Management
44 or 32 I/O Ports
4 Timers
2 Communications Interfaces
voltage FLASH) with read-out protection and
in-situ programming (remote ISP)
out protection option in ROM devices)
3 programmable levels
cillators or RC oscillators, external clock,
backup Clock Security System
Wait and Slow
one on timer A), 2 output compares (only one
on timer A), External clock input on timer A,
PWM and Pulse generator modes
patible)
Features
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
384 (256)
8K
-
-
TQFP44 / SDIP42
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
384 (256)
8K
-
512 (256)
16K
-
-40°C to +85°C (-40°C to +105/125°C optional)
Up to 8 MHz (with up to 16 MHz oscillator)
Watchdog, Two 16-bit Timers, SPI, SCI
384 (256)
TQFP64 / SDIP56
8K
-
ST72314J/N, ST72124J
– 8-bit ADC with 8 input channels (6 only on
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
– Full hardware/software development package
1 Analog Peripheral
Instruction Set
Development Tools
3.2V to 5.5V
512 (256)
ST72334Jx, not available on ST72124J2)
16K
-
PSDIP56
TQFP64
14 x 14
ADC
384 (256)
TQFP44 / SDIP42
256
8K
512 (256)
ST72334J/N,
16K
256
384 (256)
PSDIP42
TQFP44
10 x 10
TQFP64 / SDIP56
256
8K
Rev. 2.5
512 (256)
16K
256
1/153
1

Related parts for ST72C334J4T6

ST72C334J4T6 Summary of contents

Page 1

MCU WITH SINGLE VOLTAGE FLASH MEMORY, Memories – 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with read- out protection option in ROM ...

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PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 INTRODUCTION . . . . . . ...

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LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST72334J/N, ST72314J/N, ST72124J To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section 4/153 “IMPORTANT NOTES” on page 151 ...

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PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 8 or 16K FLASH/ROM Programming and Read-out protection New ADC with a better accuracy and conversion time New configurable Clock, Reset and Supply system New power saving mode ...

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ST72334J/N, ST72314J/N, ST72124J 2 INTRODUCTION The ST72334J/N, ST72314J/N and ST72124J de- vices are members of the ST7 microcontroller fam- ily. They can be grouped as follows: – ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and ...

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PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 (N versions) 64 ...

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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin SDIP Package Pinout BEEP / PF1 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 OCMP2_B / PC0 OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ...

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PIN DESCRIPTION (Cont’d) Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts PE1 / RDI AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) ...

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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to 107. Legend / Abbreviations for Table Type input output supply Input level Dedicated analog input In/Output level ...

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Pin n° Pin Name 24 V SS_3 PF0/MCO PF1/BEEP PF2 PF4/OCMP1_A PF6 (HS)/ICAP1_A ...

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ST72334J/N, ST72314J/N, ST72124J Pin n° Pin Name OSC1 DD_3 PE0/TDO PE1/RDI Notes the interrupt input column, ...

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REGISTER & MEMORY MAP As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes ...

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ST72334J/N, ST72314J/N, ST72124J REGISTER & MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR ...

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Register Address Block Label 002Ah WATCHDOG WDGCR 002Bh CRSR 002Ch Data-EEPROM EECSR 002Dh 0030h 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR ...

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ST72334J/N, ST72314J/N, ST72124J Register Address Block 0058h 006Fh 0070h ADCDR ADC 0071h ADCCSR 0072h to 007Fh Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the ...

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FLASH PROGRAM MEMORY 5.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool byte-by- byte basis. 5.2 MAIN FEATURES Remote In-Situ Programming (ISP) mode Up ...

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ST72334J/N, ST72314J/N, ST72124J 6 DATA EEPROM 6.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure ...

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DATA EEPROM (Cont’d) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 8 describes these different memory access modes. Read Operation ...

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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler. The DATA EEPROM will immediately enter this mode if there ...

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DATA EEPROM (Cont’d) 6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h Bit 7:3 = Reserved, forced by hardware to 0. Bit Interrupt enable This bit is ...

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ST72334J/N, ST72314J/N, ST72124J 7 DATA EEPROM Register Map and Reset Values Address Register 7 Label (Hex.) EECSR 002Ch 0 Reset Value 7.1 READ-OUT PROTECTION OPTION The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option 22/153 ...

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CENTRAL PROCESSING UNIT 8.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit ...

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ST72334J/N, ST72314J/N, ST72124J CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction ...

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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...

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ST72334J/N, ST72314J/N, ST72124J 9 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N, ST72314J/N and ST72124J mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing ...

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LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means ...

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ST72334J/N, ST72314J/N, ST72124J 9.2 RESET SEQUENCE MANAGER (RSM) 9.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on ...

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RESET SEQUENCE MANAGER (Cont’d) 9.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the ...

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ST72334J/N, ST72314J/N, ST72124J 9.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source 4 crystal or ceramic resonator oscillators an external RC oscillator an ...

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CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock filter control and an ...

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ST72334J/N, ST72314J/N, ST72124J 9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION Read /Write Reset Value: 000x 000x (xxh) 7 LVD Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This ...

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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...

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ST72334J/N, ST72314J/N, ST72124J INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt mapping Source N° Block RESET Reset TRAP Software Interrupt 0 Not used MCC/RTC Main Clock Controller Time Base Interrupt 1 CSS or Clock ...

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POWER SAVING MODES 11.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 19): SLOW, WAIT (SLOW WAIT), AC- ...

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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 11.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain ...

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POWER SAVING MODES (Cont’d) 11.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...

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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 11.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status ...

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I/O PORTS 12.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O ...

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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Figure 26. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION ...

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I/O PORTS (Cont’d) Table 7. I/O Port Configurations NOT IMPLEMENTED IN V TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD Notes: 1. ...

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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is ...

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I/O PORTS (Cont’d) 12.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts HALT cause the device to exit from HALT ...

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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) 12.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read /Write Reset Value: 0000 0000 (00h ...

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I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 1) 0002h PAOR 0004h PCDR 0005h PCDDR MSB 0006h PCOR ...

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ST72334J/N, ST72314J/N, ST72124J 13 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 13.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx ...

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MISCELLANEOUS REGISTERS (Cont’d) 13.3 REGISTERS DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read /Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is ...

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ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read /Write Reset Value: 0000 0000 (00h BC1 BC0 - Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits ...

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ON-CHIP PERIPHERALS 14.1 WATCHDOG TIMER (WDG) 14.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...

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ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh ...

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WATCHDOG TIMER (Cont’d) Table 12. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah 0 Reset Value ST72334J/N, ST72314J/N, ST72124J ...

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ST72334J/N, ST72314J/N, ST72124J 14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer ...

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1) See Section 13 on page 46. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0001 (01h TB1 Bit 7:4 = ...

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ST72334J/N, ST72314J/N, ST72124J 14.3 16-BIT TIMER 14.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input ...

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TIMER (Cont’d) Figure 31. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT ST7 ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte ...

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TIMER (Cont’d) Figure 32. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 33. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and ...

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TIMER (Cont’d) Figure 35. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 36. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an ...

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TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the bit is ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 38. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 39. ...

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TIMER (Cont’d) 14.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 40. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 41. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, ...

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TIMER (Cont’d) 14.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until ...

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TIMER (Cont’d) 14.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to ...

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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...

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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE ...

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TIMER (Cont’d) Table 15. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 ...

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ST72334J/N, ST72314J/N, ST72124J 14.4 SERIAL PERIPHERAL INTERFACE (SPI) 14.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 43. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register SCK SS Internal Bus DR Write MASTER CONTROL SERIAL CLOCK GENERATOR ST72334J/N, ST72314J/N, ST72124J MODF SPIF WCOL - - - SPI ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4 Functional Description Figure 42 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 45. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. ...

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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPISR SPIF 0023h Reset Value 84/153 ...

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SERIAL COMMUNICATIONS INTERFACE (SCI) 14.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 48. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU /16 86/153 Read Received Data ...

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /2 /PR /16 ...

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (32 PR with: PR ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.6 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving ...

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.8 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the ...

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs ...

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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...

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A/D CONVERTER (ADC) 14.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...

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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) 14.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If ...

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A/D CONVERTER (ADC) (Cont’d) 14.6.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...

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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 19. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 100/153 ...

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INSTRUCTION SET 15.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...

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ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d) 15.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W ...

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ST7 ADDRESSING MODES (Cont’d) 15.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...

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ST72334J/N, ST72314J/N, ST72124J 15.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic ...

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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...

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ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack ...

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ELECTRICAL CHARACTERISTICS 16.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 16.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...

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ST72334J/N, ST72314J/N, ST72124J 16.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 16.2.1 ...

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ABSOLUTE MAXIMUM RATINGS (Cont’d) 16.2.3 Thermal Characteristics Symbol T Storage temperature range STG Maximum junction temperature (see T J ING INFORMATION" on page 144 ST72334J/N, ST72314J/N, ST72124J Ratings Section 18 "DEVICE CONFIGURATION AND ORDER- ) Value Unit -65 to +150 ...

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ST72334J/N, ST72314J/N, ST72124J 16.3 OPERATING CONDITIONS 16.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 55. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALITY ...

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OPERATING CONDITIONS (Cont’d) 16.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter V Reset release threshold (V IT+ V Reset generation threshold (V IT- V LVD voltage threshold hysteresis hys 3) Vt ...

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ST72334J/N, ST72314J/N, ST72124J FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 60. High LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 Figure 61. Medium LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER ...

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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter I Supply current variation ...

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ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.2 WAIT and SLOW WAIT Modes Symbol Parameter Supply current in WAIT mode (see Figure 65) Supply current in SLOW WAIT mode (see Figure 66 Supply current in WAIT mode (see ...

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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.3 HALT and ACTIVE-HALT Modes Symbol Parameter Supply current in HALT mode I DD Supply current in ACTIVE-HALT mode 16.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over ...

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ST72334J/N, ST72314J/N, ST72124J 16.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 16.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t v(IT v(IT) c(INST) 16.5.2 External Clock ...

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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 16.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external ...

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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) 16.5.3.2 Typical Ceramic Resonators Symbol t Ceramic resonator start-up time SU(osc) Note the typical oscillator start-up time measured between V SU(OSC) quick V ramp-up from (<50 s). ...

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CLOCK AND TIMING CHARACTERISTICS (Cont’d) Table 22. Typical Ceramic Resonators f Option Byte OSC Config. (MHz) CSB1000JA 1 CSBF1000JA LP CSTS0200MGA06 2 CSTCC2.00MGA0H6 CSTS0200MGA06 2 CSTCC2.00MGA0H6 MP CSTS0400MGA06 4 CSTCC4.00MGA0H6 CSTS0400MGA06 4 CSTCC4.00MGA0H6 MS CSTS0800MGA06 8 CSTCC8.00MGA0H6 CSTS0800MGA06 8 CSTCC8.00MGA0H6 ...

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ST72334J/N, ST72314J/N, ST72124J CLOCK CHARACTERISTICS (Cont’d) 16.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator frequency f OSC External RC oscillator frequency Internal ...

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CLOCK CHARACTERISTICS (Cont’d) 16.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC f Glitch Filtered Frequency GFOSC Figure 73. Typical Safe Oscillator Frequencies fosc [kHz] -40°C 400 +25°C 350 300 250 200 3.2 VDD [V] Note: 1. ...

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ST72334J/N, ST72314J/N, ST72124J 16.6 MEMORY CHARACTERISTICS 16.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 16.6.2 EEPROM Data Memory Symbol Parameter t Programming time for 1~16 bytes prog 5) t Data retention ret 5) N Write erase ...

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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 16.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...

Page 124

ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 16.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more ...

Page 125

... GENERATOR Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. ...

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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 16.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electro- Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. The stress generally affects the ...

Page 127

EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V are ...

Page 128

ST72334J/N, ST72314J/N, ST72124J 16.8 I/O PORT PIN CHARACTERISTICS 16.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input ...

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I/O PORT PIN CHARACTERISTICS (Cont’d) 16.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 84 and Figure ...

Page 130

ST72334J/N, ST72314J/N, ST72124J I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 87. Typical V vs Vol [V] at Iio=2mA 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 Vdd [V] Figure 88. Typical V vs Ta=-40°C Vol ...

Page 131

CONTROL PIN CHARACTERISTICS 16.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Output low level voltage V ...

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ST72334J/N, ST72314J/N, ST72124J CONTROL PIN CHARACTERISTICS (Cont’d) Figure 91. Typical I vs Ion [µA] Ta=-40°C 200 Ta=25°C 150 100 50 0 3.2 3.5 4 Vdd [V] Figure 93. Typical V vs Vol [V] at Iio=2mA ...

Page 133

CONTROL PIN CHARACTERISTICS (Cont’d) 16.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 94. Two typical Applications with ISPSEL ...

Page 134

ST72334J/N, ST72314J/N, ST72124J 16.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 16.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 16.10.2 16-Bit Timer Symbol Parameter t Input ...

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COMMUNICATION INTERFACE CHARACTERISTICS 16.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for V , and T unless otherwise specified. f OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...

Page 136

ST72334J/N, ST72314J/N, ST72124J COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 96. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure ...

Page 137

COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 16.11.2 SCI - Serial Communications Interface Subject to general operating condition for V , and T unless otherwise specified Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI ...

Page 138

ST72334J/N, ST72314J/N, ST72124J 16.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization ...

Page 139

ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L Figure 99. ...

Page 140

ST72334J/N, ST72314J/N, ST72124J 17 PACKAGE CHARACTERISTICS 17.1 PACKAGE MECHANICAL DATA Figure 100. 64-Pin Thin Quad Flat Package D D1 Figure 101. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D 140/153 ...

Page 141

PACKAGE MECHANICAL DATA (Cont’d) Figure 102. 44-Pin Thin Quad Flat Package D D1 Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 104. THERMAL CHARACTERISTICS Notes: 1. The power dissipation is obtained from the formula P ...

Page 142

ST72334J/N, ST72314J/N, ST72124J Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax and P is the port power dissipation determined by the user. PORT 2. The average chip-junction temperature can be ...

Page 143

SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 105 Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 Temp. [°C] 100 PREHEATING PHASE Figure ...

Page 144

ST72334J/N, ST72314J/N, ST72124J 18 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory 2 coded versions (ROM). E PROM data memory and FLASH devices are shipped to ...

Page 145

... Figure 108. FLASH User Programmable Device Types TEMP. DEVICE PACKAGE RANGE The selected options are communicated to STMi- croelectronics using the correctly completed OP- TION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. / XXX Code name (defined by STMicroelectronics standard 0 to +70 ° industrial -40 to +85 ° ...

Page 146

... ST72P334N2T | Conditioning (specify for TQFP only): Marking Standard marking Authorized characters are letters, digits, '.', '-', '/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. Temperature Range 0°C to +70°C Clock Source Selection: Resonator: RC Network: External Clock: ...

Page 147

... DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site: http//mcu.st.com. Tools from these manufacturers include C compli- ers, emulators and gang programmers ...

Page 148

ST72334J/N, ST72314J/N, ST72124J DEVELOPMENT TOOLS (Cont’d) 18.3.1 Suggested List Of Socket Types Table 28. Suggested List of TQFP64 Socket Types Package / Probe ENPLAS TQFP64 YAMAICHI EMU PROBE YAMAICHI Suggested List of TQFP44 Socket Types Package / Probe ENPLAS TQFP44 ...

Page 149

ST7 APPLICATION NOTES IDENTIFICATION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN ...

Page 150

ST72334J/N, ST72314J/N, ST72124J IDENTIFICATION AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING ...

Page 151

IMPORTANT NOTES 19.1 SCI Baud rate registers Caution: The SCI baud rate register (SCIBRR) MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled. ST72334J/N, ST72314J/N, ST72124J 151/153 ...

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ST72334J/N, ST72314J/N, ST72124J 20 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Replaced Note by Caution in 2.5 Changed Watchdog and Halt mode Option to read “Watchdog reset on ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...

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