ST62T60CM6 STMicroelectronics, ST62T60CM6 Datasheet - Page 32

IC MCU 8BIT OTP/EPROM 20 PSOIC

ST62T60CM6

Manufacturer Part Number
ST62T60CM6
Description
IC MCU 8BIT OTP/EPROM 20 PSOIC
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T60CM6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LED, LVD, POR, WDT
Number Of I /o
13
Program Memory Size
3.8KB (3.8K x 8)
Program Memory Type
OTP
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2102-5

Available stocks

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Part Number:
ST62T60CM6
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0
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 9Interrupt Requests and Mask Bits
GENERAL
TIMER
A/D CONVERTER
AR TIMER
SPI
Port PAn
Port PBn
Port PCn
7
-
Peripheral
LES
ESB
IOR
TSCR1
ADCR
ARMC
SPIMOD
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
GEN
Register
-
-
C8h
D4h
D1h
D5h
E2h
C0h-C4h
C1h-C5h
C2h-C6h
Address
Register
-
0
-
ST6253C ST6263C ST6263B ST6260C ST6260B
GEN
ETI
EAI
OVIE
CPIE
EIE
SPIE
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
Mask bit
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the
bit to enable/disable the interrupt request.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
SPRUN: End of Transmission
PAn pin
PBn pin
PCn pin
Masked Interrupt Source
Table 9
with associated mask
I
Vector 4
Vector 4
Vector 3
Vector 2
Vector 1
Vector 1
Vector 2
Interrupt
vector
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