ST62T60CM6 STMicroelectronics, ST62T60CM6 Datasheet - Page 43

• Manufacturer Part Number: ST62T60CM6
• Description: IC MCU 8BIT OTP/EPROM 20 PSOIC
• Manufacturer: STMicroelectronics
• Series: ST6r

Specifications of ST62T60CM6

• Core Processor: ST6
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LED, LVD, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.8KB (3.8K x 8)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST62T6x
• Core: ST6
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2102-5

ST6253C ST6263C ST6263B ST6260C ST6260B
TIMER (Cont’d)
4.2.1 Timer Operation
The Timer prescaler is clocked by the prescaler
clock input (f
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#4 is generated. When the counter decrements to
Figure 27. Timer Working Principle
43/83
CLOCK
INT
0
÷ 12).
BIT0
BIT0
1
BIT1
BIT1
2
BIT2
BIT2
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT3
3
BIT3
zero, the TMZ bit in the TSCR register is set to
one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
BIT4
4
BIT4
BIT5
5
BIT5
BIT6
6
BIT6
BIT7
7
VA00186
PS0
PS1
PS2