W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet
W77E058A40DL
Specifications of W77E058A40DL
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W77E058A40DL Summary of contents
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Table of Contents- 1. GENERAL DESCRIPTION.......................................................................................................... 3 2. FEATURES.................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................. 4 4. PIN DESCRIPTION ..................................................................................................................... 5 5. FUNCTIONAL DESCRIPTION .................................................................................................... 7 6. MEMORY ORGANIZATION ........................................................................................................ 9 6.1 Program Memory............................................................................................................. 9 6.2 Data Memory................................................................................................................... 9 7. SPECIAL ...
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Clock Control................................................................................................................. 62 14. SERIAL PORT ........................................................................................................................... 63 14.1 Mode 0 .......................................................................................................................... 63 14.2 Mode 1 .......................................................................................................................... 64 14.3 Mode 2 .......................................................................................................................... 66 14.4 Mode 3 .......................................................................................................................... 67 14.5 Framing Error Detection................................................................................................ 68 14.6 Multiprocessor Communications ................................................................................... 68 15. ...
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... Programmable Watchdog Timer • Dual 16-bit Data Pointers • Software programmable access cycle to external RAM/peripherals • Packages: − Lead Free(RoHS) DIP 40: W77E058A40DL − Lead Free(RoHS) PLCC 44: W77E058A40PL − Lead Free(RoHS) PQFP 44: W77E058A40FL W77E058A Publication Release Date: April 17, 2007 - 3 - Revision A10 ...
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PIN CONFIGURATIONS 40-Pin DIP T2, P1.0 T2EX, P1.1 RXD1, P1.2 TXD1, P1.3 INT2, P1.4 INT3, P1.5 INT4, P1.6 INT5, P1.7 RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 44-Pin ...
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PIN DESCRIPTION SYMBOL TYPE EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM I EA address and data will not be present on ...
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Pin Description, continued SYMBOL TYPE PORT 3: Port bi-directional I/O port with internal pull-ups. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port 0 input TXD(P3.1) : Serial Port 0 output INT0 (P3.2) ...
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FUNCTIONAL DESCRIPTION The W77E058 is 8052 pin compatible and instruction set compatible. It includes the resources of the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and interrupt sources. The W77E058 features ...
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Timers The W77E058 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the ...
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MEMORY ORGANIZATION The W77E058 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for ...
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FFh Indirect RAM 80h 7Fh Direct RAM 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 4F ...
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SPECIAL FUNCTION REGISTERS The W77E058 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit ...
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A brief description of the SFRs now follows. Port 0 Bit: 7 P0.7 Mnemonic: P0 Port open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. Stack Pointer ...
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This is the low byte of the new additional 16-bit data pointer that has been added to the W77E058. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use ...
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Timer Control Bit: 7 TF1 Mnemonic: TCON TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear ...
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M1, M0: Mode Select bits Mode 0 0 Mode 0: 8-bits with 5-bit prescale Mode 1: 18-bits, no prescale Mode 2: 8-bits with auto-reload from THx 1 1 Mode 3: (Timer 0) TL0 is ...
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Clock Control Bit: 7 WD1 Mnemonic: CKCON WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time- out ...
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Port 1 Bit: 7 P1.7 Mnemonic: P1 P1.7-0: General purpose I/O port. Most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read. Some pins also ...
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Serial Port Control Bit: 7 SM0/FE Mnemonic: SCON SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is ...
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Poot 2 Bit: 7 P2.7 Mnemonic: P2 P2.7-0: Port bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. Port 4 Bit Mnemonic: P4 P4.3-0: Port ...
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Slave Address 1 Bit: 7 Mnemonic: SADDR1 SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated. Port 3 Bit: 7 P3.7 Mnemonic: P3 P3.7-0: General purpose ...
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Slave Address Mask Enable Bit: 7 Mnemonic: SADEN SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be ...
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This results in faster synchronous serial communication. REN_1: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled. TB8_1: This is the 9th bit to be transmitted in ...
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Power Management Register Bit CD1 CD0 Mnemonic: PMR CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one machine cycle. There are three modes including divide 1024. Switching ...
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LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. XTUP:Crystal Oscillator Warm-up Status. when set, this bit indicates CPU ...
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RCLK: Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data in serial modes then timer 1 overflow is used for baud rate generation, otherwise timer 2 overflow is ...
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Timer 2 Capture LSB Bit RCAP2L.7 RCAP2L.6 Mnemonic: RCAP2L RCAP2L:This register is used to capture the TL2 value when a timer 2 is configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload ...
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RS.1-0: Register bank select bits: RS1 RS0 Register bank OV: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of ...
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Extended Interrupt Enable Bit Mnemonic: EIE EIE.7-5:Reserved bits, will read high EWDI: Enable Watchdog timer interrupt EX5: External Interrupt 5 Enable. EX4: External Interrupt 4 Enable. EX3: External Interrupt 3 Enable. EX2: External Interrupt 2 Enable. B Register ...
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INSTRUCTION The W77E058 executes all the instructions of the standard 8032 family. The operation of these instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of these instructions is different. The ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION OP-CODE ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC A, ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION BYTES OP-CODE CJNE R5, #data, rel BD CJNE R6, #data, rel BE CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION BYTES OP-CODE INC R6 0E INC R7 0F INC @R0 06 INC @R1 07 INC direct 05 INC DPTR A3 JMP @A+DPTR 73 JZ rel 60 JNZ rel 70 JC rel ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION BYTES OP-CODE MOV R1, direct A9 MOV R2, direct AA MOV R3, direct AB MOV R4, direct AC MOV R5, direct AD MOV R6, direct AE MOV R7, direct AF MOV ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION BYTES OP-CODE MOVX A, @R0 E2 MOVX A, @R1 E3 MOVX A, @DPTR E0 MOVX @R0 MOVX @R1 MOVX @DPTR MOV C, bit A2 MOV ...
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Table 3. Instruction Timing for W77E058, continued HEX INSTRUCTION BYTES OP-CODE SUBB SUBB SUBB SUBB SUBB SUBB SUBB A, @R0 96 SUBB ...
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Instruction Timing The instruction timing for the W77E058 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between ...
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Instruction Fetch CLK ALE PSEN PC AD7-0 Address A15-8 PORT 2 Figure 4. Two Cycle Instruction Timing Instruction Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 PORT 2 Address A15-8 Figure 5. Three Cycle ...
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Instruction Fetch CLK ALE PSEN OP-CODE AD7-0 A7-0 Port 2 Address A15-8 Figure 6. Four Cycle Instruction Timing Instruction Fetch Operand Fetch CLK ALE PSEN A7-0 OP-CODE A7-0 AD7-0 ...
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MOVX Instruction The W77E058, like the standard 8032, uses the MOVX instruction to access external Data Memory. This Data Memory includes both off-chip memory as well as memory mapped peripherals. While the results of the MOVX instruction are the ...
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Machine cycles in standard 8032 = 10 + (26 * CNT) Machine cycles in W77E058 = 10 + (26 * CNT) If CNT = 50 Clock cycles in standard 8032= ((10 + (26 *50 (10 + 1300) ...
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MOVX instructions that last from machine cycles in length. Note that the stretching of the instruction only results in the elongation of the MOVX instruction the state of the ...
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Last Cycle First of Previous Machine Cycle Instruction CLK ALE PSEN WR A0-A7 D0-D7 A0-A7 PORT 0 MOVX Inst. Next Inst. Address Address MOVX Inst. PORT 2 A15-A8 A15-A8 Figure 9. Data Memory Write ...
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Wait State Control Signal Either with the software using stretch value to change the required machine cycle of MOVX instruction, the W77E058 provides another hardware signal WAIT to implement the wider duration of external data access timing. This wait ...
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POWER MANAGEMENT The W77E058 has several features that help the user to control the power consumption of the device. The power saving features are basically the POWER DOWN mode, ECONOMY mode and the IDLE mode of operation. 9.1 Idle ...
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The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching to divide 1024 mode must first go from divide by 4 mode. This means software can not switch directly ...
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Power Down mode and continues from there. When RGSL(EXIF.1) bit is set to 1, the CPU will use the internal RC oscillator instead of crystal to exit Power Down mode. The microcontroller will automatically switch from RC ...
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RESET CONDITIONS The user has several hardware related options for placing the W77E058 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state ...
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Table 6. SFR Reset Value SFR NAME RESET VALUE P0 11111111b SP 00000111b DPL 00000000b DPH 00000000b DPL1 00000000b DPH1 00000000b DPS 00000000b PCON 00xx0000b TCON 00000000b TMOD 00000000b TL0 00000000b TL1 00000000b TH0 00000000b TH1 00000000b CKCON 00000001b P1 ...
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INTERRUPTS The W77E058 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or ...
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Priority Level Structure There are three priority levels for the interrupts, highest, high and low. The interrupt sources can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower ...
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The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will ...
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Interrupt Response Time The response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. In the case of external interrupts INT0 to INT5 , they are sampled at ...
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PROGRAMMABLE TIMERS/COUNTERS The W77E058 has three 16-bit programmable timer/counters and one programmable Watchdog timer. The Watchdog timer is operationally quite different from the other two timers. 12.1 Timer/Counters 0 & 1 The W77E058 has two 16-bit Timer/Counters. Each of ...
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set to 1, then it will count transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When the 13 bit count reaches 1FFFh the next count will cause ...
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T0M = CKCON.3 (T1M = CKCON.4) Clock Source Mode input 1/4 div osc/1 1 div osc/16 div. by 1024 osc/256 0 1/ P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = ...
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Timer/Counter 2 Timer/Counter bit up/down counter which is configured by the T2MOD register and controlled by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer 0 and Timer 1 ...
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T2M = CKCON.5 Clock Source 1/4 1 Mode input div osc/1 div osc/16 div. by 1024 osc/256 1/ P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 12.3.2 Auto-Reload Mode, Counting up ...
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Auto-Reload Mode, Counting Up/Down Timer/Counter 2 will be in auto-reload mode as an up/down counter cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter up/down counter whose direction is ...
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Programmable Clock-out Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software must initiate ...
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WACHDOG TIMER The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer basically a set of dividers that divide the ...
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Now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. If any errant code is executed now, then ...
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Watchdog Control WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the global interrupt enable is ...
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SERIAL PORT Serial port in the W77E058 is a full duplex port. The W77E058 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports are capable of synchronous as ...
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Clock Source Mode input div osc/1 div osc/16 div. by 1024 osc/256 Write to SBUF START TX CLOCK SM2 SERIAL 0 1 CONTROLLE RX CLOCK RI RX START REN RXD P3.0 Alternate Iutput ...
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The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. ...
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Mode 2 This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a programmable 9th ...
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SBUF and RB8 are loaded and RI is set. However certain conditions must be met before the loading and setting of RI can be done. ...
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Table 10. Serial Ports Modes SM1 SM0 MODE TYPE Synch Asynch Asynch Asynch. 14.5 Framing Error Detection A Frame Error occurs when a valid stop bit is not ...
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SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives the user flexibility to address ...
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TIMED ACCESS PROTECTION The W77E058 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If left unprotected, errant ...
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Example 5: Invalid Access MOV TA, #0AAh 3 M/C NOP 1 M/C MOV TA, #055h 3 M/C SETB EWT 2 M/C In the first two examples, the writing to the protected bits is done before the 3 machine cycle window ...
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ON-CHIP FLASH EPROM CHARACTERISTICS The W77E058 has several modes to program the on-chip Flash EPROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and V P1.7−P1.0) ...
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P3.0 P3.1 P3.2 OPERATIONS (A9 (A13 (A14 CTRL) CTRL) CTRL) Read Output Disable Program Program Verify Erase Erase Verify Program/Erase X 0 ...
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Security Bits During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those ...
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B0: Lock bit This bit is used to protect the customer's program code in the W77E058. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash ...
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ELECTRICAL CHARACTERISTICS 17.1 Absolute Maximum Ratings SYMBOL PARAMETER DD − DC Power Supply V Input Voltage V Operating Temperature T Storage Temperatute Tst Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life ...
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D.C. Characteristics, continued. PARAMETER SYMBOL Output Low Voltage V OL1 P1, P2, P3 Output Low Voltage V OL2 [*2] P0, ALE, PSEN Output High Voltage V OH1 P1, P2, P3 Output High Voltage V OH2 [*2] P0, ALE, PSEN Notes: ...
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AC Specification PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low Address Hold After ALE Low for MOVX Write ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width ...
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MOVX Characteristics Using Strech Memory Cycles PARAMETER SYMBOL Data Access ALE Pulse Width t Address Hold After ALE Low for t MOVX write t RD Pulse Width t WR Pulse Width t RD Low to Valid Data In Data Hold ...
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Explanation of Logic Symbols In order to maintain compatibility with the original 8051 family, this device specifies the same parameter for each ...
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Program Memory Read Cycle t LHLL ALE t AVLL PSEN t LLAX1 ADDRESS PORT 0 A0-A7 t AVIV1 t AVIV2 PORT 2 ADDRESS A8-A15 Data Memory Read Cycle ALE PSEN t LLAX1 t RD PORT 0 INSTRUCTION ADDRESS IN PORT ...
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Data Memory Write Cycle ALE PSEN t LLAX2 t WR PORT 0 ADDRESS INSTRUCTION IN PORT 2 t LLWL t WLWH AVLL t AVWL1 t WHQX t QVWX DATA OUT A0-A7 t AVDV2 ADDRESS A8-A15 - 82 - W77E058A t ...
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TYPICAL APPLICATION CIRCUITS 18.1 Expanded External Program Memory and Crystal XTAL1 XTAL2 CRYSTAL 8 RST C1 C2 INT0 12 13 INT1 ...
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Expanded External Data Memory and Oscillator XTAL1 OSCILLATOR XTAL2 8 RST INT0 12 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 ...
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PACKAGE DIMENSIONS 19.1 40-pin DIP 19.2 44-pin PLCC θ e ...
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QFP See Detail F y Seating Plane Dimension in inch Symbol Min. Nom. Max. A --- --- A ...
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VERSION HISTORY VERSION DATE PAGE A1 Aug. 2001 A2 Sep. 2001 A3 Mar. 2002 A4 May. 2004 A5 June, 2004 A6 Feb. 17, 2005 A7 April 18, 2005 A8 September 29, 2006 A9 November 7, 2006 A10 April 17, ...