MCU ARM 32BIT 384K FLASH 100LQFP

STM32F101VDT6

Manufacturer Part NumberSTM32F101VDT6
DescriptionMCU ARM 32BIT 384K FLASH 100LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101VDT6 datasheet
 


Specifications of STM32F101VDT6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o80
Program Memory Size384KB (384K x 8)Program Memory TypeFLASH
Ram Size48K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-LQFP
Processor SeriesSTM32F101xCoreARM Cortex M3
Data Bus Width32 bitData Ram Size48 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os80Number Of Timers6
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2Development Tools By SupplierSTM3210E-EVAL
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 16 Channel
On-chip Dac12 bit, 2 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
Eeprom Size-For Use With497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Description
2.3.7
Nested vectored interrupt controller (NVIC)
The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested
vectored interrupt controller able to handle up to 60 maskable interrupt channels (not
including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.8
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
2.3.9
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock is available when necessary (for example with failure
of an indirectly used external oscillator).
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and
APB domains is 36 MHz. See
2.3.10
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
16/106
STM32F101xC, STM32F101xD, STM32F101xE
Figure 2
for details on the clock tree.
Doc ID 14610 Rev 7