MCU ARM 32BIT 384K FLASH 100LQFP

STM32F101VDT6

Manufacturer Part NumberSTM32F101VDT6
DescriptionMCU ARM 32BIT 384K FLASH 100LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101VDT6 datasheet
 


Specifications of STM32F101VDT6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o80
Program Memory Size384KB (384K x 8)Program Memory TypeFLASH
Ram Size48K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-LQFP
Processor SeriesSTM32F101xCoreARM Cortex M3
Data Bus Width32 bitData Ram Size48 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os80Number Of Timers6
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2Development Tools By SupplierSTM3210E-EVAL
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 16 Channel
On-chip Dac12 bit, 2 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
Eeprom Size-For Use With497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Electrical characteristics
Table 32.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
t
FSMC_NE low time
w(NE)
t
FSMC_NEx low to FSMC_NWE low
v(NWE_NE)
t
FSMC_NWE low time
w(NWE)
t
FSMC_NWE high to FSMC_NE high hold time
h(NE_NWE)
t
FSMC_NEx low to FSMC_A valid
v(A_NE)
t
Address hold time after FSMC_NWE high
h(A_NWE)
t
FSMC_NEx low to FSMC_BL valid
v(BL_NE)
t
FSMC_BL hold time after FSMC_NWE high
h(BL_NWE)
t
FSMC_NEx low to Data valid
v(Data_NE)
t
Data hold time after FSMC_NWE high
h(Data_NWE)
t
FSMC_NEx low to FSMC_NADV low
v(NADV_NE)
t
FSMC_NADV low time
w(NADV)
1. C
= 15 pF.
L
2. Based on characterization, not tested in production.
Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms
FSMC_NE
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_NADV
58/106
STM32F101xC, STM32F101xD, STM32F101xE
Parameter
3T
T
HCLK
T
HCLK
T
HCLK
T
HCLK
T
HCLK
T
HCLK
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
v(A_NE)
Address
t
v(BL_NE)
NBL
t
su(Data_NE)
t
t
v(A_NE)
su(Data_NOE)
Address
Data
t
t
v(NADV_NE)
h(AD_NADV)
t
w(NADV)
Doc ID 14610 Rev 7
(1)(2)
Min
Max
Unit
– 1
3T
+ 2
ns
HCLK
HCLK
– 0.5
T
+ 1.5
ns
HCLK
– 0.5
T
+ 1.5
ns
HCLK
ns
7.5
ns
ns
1.5
ns
– 0.5
ns
T
+ 7
ns
HCLK
ns
5.5
ns
T
+ 1.5
ns
HCLK
t
h(NE_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
h(Data_NE)
t
h(Data_NOE)
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