STM32F101ZCT6 STMicroelectronics, STM32F101ZCT6 Datasheet - Page 105

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STM32F101ZCT6

Manufacturer Part Number
STM32F101ZCT6
Description
MCU ARM 32BIT 256K FLASH 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101ZCT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
112
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
A/d Bit Size
12 bit
A/d Channels Available
16
Height
1.4 mm
Length
20 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Width
20 mm
For Use With
497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
STM32F101xC, STM32F101xD, STM32F101xE
Table 65.
24-Sep-2009
21-Jul-2009
Date
Document revision history (continued)
Revision
6
7
Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access
line block diagram
Note 5
STM32F101xx pin
V
voltage.
f
characteristics.
Table 23: HSE 4-16 MHz oscillator characteristics
modified below
Figure 40: Recommended NRST pin protection
replaced by C in
Table 24: LSE oscillator characteristics (fLSE = 32.768
modified and moved below the tables.
Table 25: HSI oscillator characteristics
from
Jitter added to
In
timings: t
In
timings: t
In
t
In
t
In
t
In
cycles: t
Table 52: SPI characteristics
C
R
Table 57: DAC characteristics
buffered DAC
Number of DACs corrected in
I
consumptions in Stop and Standby
Figure 13: Typical current consumption on VBAT with RTC on vs.
temperature at different VBAT values
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in
Table 57: DAC characteristics
Small text changes.
HSE_ext
h(AD_NADV)
h(A_NWE)
h(CLKH-NWAITV)
DD_VBAT
RERINT
ADC
AIN
Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
Table 33: Asynchronous multiplexed NOR/PSRAM read
Table 34: Asynchronous multiplexed NOR/PSRAM write
Table 35: Synchronous multiplexed NOR/PSRAM read
Table 40: Switching characteristics for NAND Flash read and write
Doc ID 14610 Rev 7
Table 27: Low-power mode wakeup
max values modified in
and R
updated and
h(NOE-D)
min modified in
and T
h(BL_NOE)
h(A_NWE)
updated in
modified.
and t
AIN
added.
Coeff
Table 28: PLL
Figure 19: Typical application with an 8 MHz
Section 5.3.11: EMC characteristics on page
modified.
parameters modified in
Table 23: HSE 4-16 MHz oscillator characteristics
h(A_NOE)
modified.
and t
modified.
definitions.
and t
added to
Note 4
Table 17: Typical and maximum current
h(Data_NWE)
h(A_NOE)
Table 21: High-speed external user clock
modified.
added in
Table 54: RAIN max for fADC = 14
Table 13: Embedded internal reference
modified.
characteristics.
Table 3: STM32F101xx
modified.
modified.
Changes
modified.
modified.
modes.
Table 5: High-density
added.
modified. Conditions removed
Table 53: ADC
Figure 49: 12-bit buffered /non-
timings.
modified. C
modified.
Revision history
family.
characteristics.
kHz), notes
timings:
timings:
timings:
L1
Note 1
crystal.
75.
and C
MHz.
105/106
and
L2

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