MCU ARM9 2048KB FLASH 128LQFP

 

STR912FAW47X6T

Manufacturer Part NumberSTR912FAW47X6T
DescriptionMCU ARM9 2048KB FLASH 128LQFP
ManufacturerSTMicroelectronics
SeriesSTR9
STR912FAW47X6T datasheets

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Specifications of STR912FAW47X6T

Core ProcessorARM9Core Size32-Bit
Speed96MHzConnectivityCAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
PeripheralsBrown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDTNumber Of I /o80
Program Memory Size2MB (2M x 8)Program Memory TypeFLASH
Ram Size96K x 8Voltage - Supply (vcc/vdd)1.65 V ~ 2 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case128-LQFP
Processor SeriesSTR912xCoreARM966E-S
Data Bus Width16 bit, 32 bitData Ram Size96 KB
Interface TypeCAN, I2C, IrDA, SSP, UART, USBMaximum Clock Frequency96 MHz
Number Of Programmable I/os80Number Of Timers4
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2Minimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelFor Use WithMCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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STR91xFAxxx
The STR91xFA MAC includes the following features:
●
Supports 10 and 100 Mbps rates
●
Tagged MAC frame support (VLAN support)
●
Half duplex (CSMA/CD) and full duplex operation
●
MAC control sublayer (control frames) support
●
32-bit CRC generation and removal
●
Several address filtering modes for physical and multicast address (multicast and group
addresses)
●
32-bit status code for each transmitted or received frame
●
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words
(32 bits each), and the receive FIFO is 16 words deep.
A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-
speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
●
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
●
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
●
Open and Closed descriptor chain management
3.18
USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and
Data Link layers for direct bus connection by an external USB host on pins USBDP and
USBPN. The USB interface detects token packets, handles data transmission and
reception, and processes handshake packets as required by the USB 2.0 standard.
The USB slave interface includes the following features:
●
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB
2.0 specification
●
Supports isochronous, bulk, control, and interrupt endpoints
●
Configurable number of endpoints allowing a mixture of up to 20 single-buffered
monodirectional endpoints or up to 10 double-buffered bidirectional endpoints
●
Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is
connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects
to the other SRAM port.
●
CRC generation and checking
●
NRZI encoding-decoding and bit stuffing
●
USB suspend resume operations
Doc ID 13495 Rev 6
Functional overview
31/102

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