ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet

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... Up to 111 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power-down and stand-by modes ■ Single voltage supply ± (embedded regulator for 1.8 V core supply) ■ Temperature range: -40 to +125 °C Rev 2 ST10F272M LQFP144 1.4mm 1/176 www.st.com 1 ...

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... Flash data register 0 low (FDR0L Flash data register 0 high (FDR0H Flash data register 1 low (FDR1L Flash data register 1 high (FDR1H Flash address register low (FARL Flash address register high (FARH Flash error register (FER Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash non-volatile write protection I register (FNVWPIR ST10F272M ...

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... ST10F272M 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 43 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 Alternate and selective boot mode (ABM and SBM 6.3.1 6.3.2 6 ...

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... System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 20.3 Synchronous reset (warm reset 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4/176 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ST10F272M ...

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... ST10F272M 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21.2.1 21.2.2 21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 21.3.1 21.3.2 21.3.3 21.3.4 22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 107 23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 23 ...

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... Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6/176 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Oscillator watchdog (OWD 143 Phase locked loop (PLL 144 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 ST10F272M ...

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... Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 23. X-bus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 37 Table 24. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 25. Flash write operations Table 26. ST10F272M boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 27. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 28. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 29. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 30. ...

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... External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 74. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 75. SSC slave mode timings 169 Table 76. PQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 77. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 78. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 79. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8/176 = 5 V ± ST10F272M = -40 to +125 ° 148 A ...

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... Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 44. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 45. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 46. ST10F272M PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 47. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 48. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 49. External clock drive XTAL1 151 Figure 50 ...

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... CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 59. External bus arbitration (releasing the bus 166 Figure 60. External bus arbitration (regaining the bus 167 Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 63. PQFP144 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 64. LQFP144 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10/176 ST10F272M ...

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... Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F272M is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work ...

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... Introduction Figure 1. Logic symbol 12/176 XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F272M NMI EA/V STBY READY ALE RD WR/WRL Port 5 16-bit ST10F272M Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD ...

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... P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 ST10F272M Pin data 108 P0H.0 / AD8 107 P0L.7 / AD7 106 P0L.6 / AD6 105 P0L.5 / AD5 104 P0L ...

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... CAPCOM2: CC20 capture input/compare output P8.5 CC21IO CAPCOM2: CC21 capture input/compare output P8.6 CC22IO CAPCOM2: CC22 capture input compare output RxD1 ASC1: Data input (asynchronous) or I/O (synchronous) P8.7 CC23IO CAPCOM2: CC23 capture input/compare output TxD1 ASC1: Clock/data output (asynchronous/synchronous) ST10F272M Function ...

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... ST10F272M Table 1. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5. 47-54 I/O 57-64 47 I/O ... ... P2.0 - P2.7 54 I/O P2.8 - P2.15 57 I/O I ... ... 64 I 8-bit bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state ...

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... RxD0 ASC0: data input (asynchronous) or I/O (synchronous) P3.12 BHE External memory high byte enable signal WRH External memory high byte write strobe P3.13 SCLK0 SSC0: master clock output/slave clock input System clock output P3.15 CLKOUT (programmable divider on CPU clock) ST10F272M Function ...

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... ST10F272M Table 1. Pin description (continued) Symbol Pin Type 85-92 I P4.0 - P4 WR/WRL 96 O READY READY ALE 98 O Port 8-bit bidirectional I/O port bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS) ...

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... O 18/176 External access enable pin. A low level applied to this pin during and after reset forces the ST10F272M to start the program from the external memory space. A high level forces ST10F272M to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F272M under reset and main V ...

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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power-down) instruction is executed, the NMI pin must be low in order to force the ST10F272M to go into power-down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...

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... Functional description 3 Functional description The architecture of the ST10F272M combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F272M. Figure 3. Block diagram XRAM1 ...

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... ST10F272M 4 Memory organization The memory space of the ST10F272M is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable ...

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... XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I accesses are possible). Two waitstates give an access time of 100 MHz CPU clock. No tristate waitstate is used. 22/176 2 C module use demultiplexed addresses and a 16-bit data bus (only word ST10F272M module access. The ...

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... Mbytes of external memory can be connected to the microcontroller. Visibility of XBUS peripherals In order to keep the ST10F272M compatible with the ST10F168/ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the ...

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... Memory organization Figure 4. ST10F272M on-chip memory mapping (ROMEN = 1/XADRS = 800Bh - reset value) Code Data Code segment page segment FF FFFF 1023 11 FFFF 255 17 11 0000 10 FFFF 16 10 0000 0F FFFF 15 0F 0000 0E FFFF 14 0E 0000 0D FFFF 13 0D 0000 0C FFFF 12 0C 0000 0B FFFF 11 0B 0000 ...

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... ST10F272M 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed of one matrix module, 256 Kbytes wide. This module is called IFlash because the ST10 internal bus. Figure 5. Flash structure The programming operations of the Flash are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are generated internally ...

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... FFFF 0x0002 0000 - 0x0002 FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF ST10F272M operations)), and when accessed in write Size ST10 bus size (bytes ...

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... ST10F272M Table 5 above refers to the configuration when bit ROMS1 of SYSCON register is set. Refer to the device user manual for more details on the memory mapping during bootstrap mode. In particular, when bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● ...

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... Moreover, the test-Flash block is seen by the user in bootstrap mode only. FCR0L (0x08 0000 28/176 During a write operation, when bit LOCK of FCR0 is set forbidden to write into the Flash control registers. FCR Reserved - ST10F272M Reset value: 0000h LOCK Reserved BSY0 Res ...

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... ST10F272M Table 7. Flash control register 0 low Bit Name Flash registers access locked When this bit is set, it means that the access to the Flash control registers FCR0H/- FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective ...

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... Flash data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range of 0x0E8FB0 to 0x08DFBF. SPR bit is automatically reset at the end of the set protection operation. 30/176 Function ST10F272M ...

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... ST10F272M 5.4.3 Flash control register 1 low (FCR1L) The Flash control register 1 Low (FCR1L), together with Flash control register 1 high (FCR1H), is used to select the sectors to erase, or during any write operation to monitor the status of each sector and bank. FCR1L (0x08 0004 Table 9. Flash control register 1 low ...

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... These bits must be written with the data to program the Flash with the following operations: Word program (32-bit), double word program (64-bit) and set protection. B0Fy = 1 meaning Erase error in sector y of bank0 Erase suspended in sector y of bank0 Don’t care Reset value: FFFFh Function Reset value: FFFFh Function ST10F272M ...

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... ST10F272M 5.4.7 Flash data register 1 low (FDR1L) FDR1L (0x08 000C DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 Table 14. Flash data register 1 low Bit Name Data Input 15:0 15:0 DIN[15:0] These bits must be written with the data to program the Flash with the following operations: Word program (32-bit), double word program (64-bit) and set protection ...

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... This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset. Reset value: 0000h ADD20 ADD19 ADD18 ADD17 ADD16 Function Reset value: 0000h Function ST10F272M ...

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... ST10F272M Table 18. Flash error register (continued) Bit Name 6 SEQER 7 RESER 8 WPF 5.5 Protection strategy The protection bits are stored in non-volatile Flash cells inside IFlash module, that are read once at reset and stored in four volatile registers. Before they are read from the non-volatile cells, all the available protections are forced active during reset ...

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... RW RW 36/176 NVR Reserved W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 - RW Write protection bank 0/sectors 7-0 (IFlash) These bits, if programmed at 0, disable any write access to the sectors of bank 0 (IFlash) NVR Reserved - NVR ST10F272M Reset value: FFFFh Function Delivery value: ACFFh Function Delivery value: FFFFh DBGP ACCP RW RW ...

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... ST10F272M Table 21. Flash non-volatile access protection register 1 low Bit Name Protections disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP 15:0 PDS[15:0] is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0 ...

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... Fetching from IRAM Fetching from XRAM Fetching from external memory 38/176 Section 5.5.9: Temporary Read XRAM or Read IFlash / external memory/ jump to IFlash jump to XRAM or external memory Yes/yes Yes/yes No/yes Yes/yes No/yes Yes/yes No/yes Yes/yes ST10F272M unprotection). Read Flash Write Flash registers registers Yes ...

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... ST10F272M When the access protection is enabled, Flash registers can not be written program/erase operation can be run on IFlash. To enable the access to registers again, the temporary access unprotection procedure has to be followed (see 5.5.8 Write protection The Flash modules have one level of write protections: each sector of each bank of each Flash module can be software write protected by programming at 0 the related bit W0Px in FNVWPIRL register ...

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... DWPG/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Load Data in FDR1L*/ /*Load Data in FDR1H*/ /*Operation start*/ /*Set SER in FCR0H*/ /*Set B0F1, B0F0*/ /*Operation start*/ /*Set SUSP in FCR0H*/ /*Set SER in FCR0H*/ /*Operation resume*/ ST10F272M ...

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... ST10F272M Set protection Example 1: Enable write protection of sectors B0F3-0 of Bank 0 in IFlash module. FCR0H |= 0x0100; FARL = 0xDFB4; FARH = 0x0008; FDR0L = 0xFFF0; FDR0H = 0xFFFF; FCR0H |= 0x8000; Example 2: Enable access and debug protection. FCR0H |= 0x0100; FARL = 0xDFB8; FARH = 0x0008; FDR0L = 0xFFFC; FCR0H |= 0x8000; ...

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... WPG DWPG SER SPR SUSP Start write operation FCR0L.LOCK == 0? Yes Write operation finished? (1) (Check related bits ) Yes Check error status No error: Proceed with application ST10F272M Table 25. Start bit FARL/FARH WMS FDR0L/FDR0H FARL/FARH FDR0L/FDR0H WMS FDR1L/FDR1H FCR1L/FCR1H WMS FDR0L/FDR0H WMS None None ...

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... Standard bootstrap loader After entering the standard BSL mode and the respective initialization, the ST10F272M scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line. Start condition on UART RxD: ST10F272M starts standard bootstrap loader. This bootstrap loader is identical to that of other ST10 devices (example: ST10F269, ST10F168) ...

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... P0L.4 low at reset), additional check is made. Depending on the value at the user key location, the following behavior occurs: ● A jump is performed to the standard bootstrap loader ● Only UART is enabled for bootstrapping ● Only CAN1 is enabled for bootstrapping ● The device enters an infinite loop 44/176 ST10F272M ...

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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F272M’s instructions can be executed in one instruction cycle which requires MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...

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... Interrupt controller ST10 CPU 1. Shared with standard ALU 46/176 Operand 1 16 signed/unsigned Concatenation 32 Mux Sign extend MRW Scaler Repeat unit Mux 40 MCW A 40-bit signed arithmetic unit MSW Flags MAE Control unit ST10F272M Operand multiplier 32 08000h Mux MAH MAL 40 8-bit left/right shifter ...

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... ST10F272M 7.2 Instruction set summary Table 27 lists the instructions of the ST10F272M. The detailed description of each instruction can be found in the ST10 family programming manual. Table 27. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) ...

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... Enter idle mode Enter power-down mode (supposes NMI-pin being low) Service watchdog timer Disable watchdog timer Signify end-of-initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended register sequence Begin EXTended page (and register) sequence Begin EXTended segment (and register) sequence Null operation ST10F272M Bytes ...

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... ST10F272M 7.3 MAC co-processor specific instructions Table 28 lists the MAC instructions of the ST10F272M. The detailed description of each instruction can be found in the ST10 family programming manual. Note that all MAC instructions are encoded on 4 bytes. Table 28. MAC instruction set summary Mnemonic CoABS ...

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... The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. 50/176 ST10F272M ...

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... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F272M has eight PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...

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... T1IE T1INT T7IR T7IE T7INT T8IR T8IE T8INT T2IR T2IE T2INT T3IR T3IE T3INT T4IR T4IE T4INT T5IR T5IE T5INT ST10F272M Vector Trap location number 00’0058h 16h 00’005Ch 17h 00’0060h 18h 00’0064h 19h 00’0068h 1Ah 00’006Ch 1Bh 00’0070h 1Ch 00’0074h 1Dh 00’ ...

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... ST10F272M Table 29. Interrupt sources (continued) Source of interrupt or PEC service request GPT2 timer 6 GPT2 CAPREL register A/D conversion complete A/D overrun error ASC0 transmit ASC0 transmit buffer ASC0 receive ASC0 error SSC transmit SSC receive SSC error PWM channel 0...3 See Section 9.1 See Section 9 ...

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... Interrupt source CAN1 interrupt CAN2 interrupt receive transmit error SSC1 receive SSC1 transmit SSC1 error ASC1 receive ASC1 transmit ASC1 transmit buffer ASC1 error PLL unlock/OWD PWM1 channel 3...0 54/176 7 0 Flag[7:0] XIRxSEL[7: Enable[7:0] XIRxSEL[15: XP0INT ST10F272M XPxIC.XPxIR ( XP1INT XP2INT XP3INT ...

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... ST10F272M 9.2 Exception and error traps list Table 31 shows all of the possible exceptions or error conditions that can arise during run- time. Table 31. Trap priorities Exception condition Reset functions: Hardware reset Software reset Watchdog timer overflow Class A hardware traps: Non-maskable interrupt Stack overflow ...

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... Capture/compare (CAPCOM) units 10 Capture/compare (CAPCOM) units The ST10F272M has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), digital to analog (D/A) conversion, software timing, or time recording relative to external events ...

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... ST10F272M Table 32. Compare modes Compare modes Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set ‘ ...

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... The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. 58/176 ST10F272M ...

Page 59

... ST10F272M Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz MHz CPU 000b Prescaler factor 8 Input frequency 5 MHz 2.5 MHz Resolution 200 ns Period maximum 13.1 ms 26.2 ms Figure 10. Block diagram of GPT1 T2EUD n CPU clock 2 T2IN n CPU clock 2 T3IN T3EUD T4IN n CPU clock ...

Page 60

... Timer input selection T5I/T6I 010b 011b 100b 2.5 MHz 1.25 MHz 625 kHz 400 ns 0.8 µs 1.6 µs 26.2 ms 52.4 ms 104.8 ms 101b 110b 64 128 256 312.5 kHz 156.25 kHz 3.2 µs 6.4 µs 209.7 ms 419.4 ms ST10F272M 111b 512 78.125 kHz 12.8 µs 838.9 ms ...

Page 61

... ST10F272M Figure 11. Block diagram of GPT2 T5EUD CPU clock T5IN CAPIN T6IN CPU clock T6EUD n 2 n=2...9 T5 mode GPT2 timer T5 control Clear Capture GPT2 CAPREL T6 mode GPT2 timer T6 control n 2 n=2...9 General purpose timer unit U/D Interrupt request Interrupt request Reload ...

Page 62

... PWM modules 12 PWM modules Two pulse width modulation modules are available on ST10F272M: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or center-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. ...

Page 63

... I/O’s special features 13.2.1 Open drain mode Some of the I/O ports of ST10F272M support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to provide an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective open drain control registers ODPx ...

Page 64

... Parallel ports 13.2.2 Input threshold control The standard inputs of the ST10F272M determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...

Page 65

... ST10F272M This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of port0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data ...

Page 66

... The ST10F272M has 16+8 multiplexed input channels on port 5 and port 1. The selection between port 5 and port 1 is made via a bit in an X-bus register. Refer to the user manual for a detailed description. ...

Page 67

... ST10F272M ● Auto scan continuous conversion: The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated ...

Page 68

... Asynchronous/synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F272M and other microcontrollers, microprocessors or external peripherals. 15.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...

Page 69

... ST10F272M 15.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F272M. Half-duplex communication Mbaud (at 40 MHz of f mode. Table 38. ASC synchronous baudrates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baudrate (baud) Deviation error Reload value (hex) Baudrate (baud) Deviation error Reload value (hex) 5 000 000 0 ...

Page 70

... Synchronous baudrate and reload values (f Reserved Can be used only with f 6.6 Mbaud 5 Mbaud 2.5 Mbaud 1 Mbaud 100 Kbaud 10 Kbaud 1 Kbaud 306 baud 70/176 Baudrate = 32 MHz (or lower) CPU ST10F272M = 40 MHz) CPU Bit time Reload value - 0000h - 0001h 150 ns 0002h 200 ns 0003h 400 ns 0007h 1 µ ...

Page 71

... ST10F272M interface 2 The integrated I C bus module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s ...

Page 72

... XMISCEN of the XPERCON register and bit XPEN of the SYSCON register. 17.2 CAN bus configurations Depending on the application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F272M can support both configurations. 72/176 21. ST10F272M ...

Page 73

... Figure 13. Connection to single CAN bus via separate CAN transceivers CAN_H CAN_L The ST10F272M also supports single CAN bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment ...

Page 74

... CAN modules 17.2.2 Multiple CAN bus The ST10F272M provides two CAN interfaces to support the kind of bus configuration in Figure 15. Figure 15. Connection to two different CAN buses (example, gateway application) CAN_H CAN_L 17.2.3 Parallel mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16 ...

Page 75

... ST10F272M 18 Real-time clock The real-time clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can continue running even in Idle or power-down modes (if so enabled). Registers access is implemented onto the XBUS. This module is designed with the following characteristics: ● ...

Page 76

... For security, rewrite WDTCON each time before the watchdog timer is serviced Table 40 shows the watchdog time range for 40 MHz CPU clock. Table 40. WDTREL reload value (f Reload value in WDTREL FFh 00h 76/176 = 40 MHz) CPU Prescaler for MHz CPU 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) 12.8 µs 3.277 ms ST10F272M 819.2 µs 209.7 ms ...

Page 77

... ST10F272M 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 41. Reset event definition Reset source Power-on reset Asynchronous hardware reset Synchronous long hardware ...

Page 78

... Section 24: Electrical ST10F272M does not need a stabilized clock signal to detect an asynchronous reset suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on port0 is settled ...

Page 79

... ST10F272M Warning: In figures 17 and from internal or external memory respectively, highlighting the reset phase extension introduced by the embedded Flash module when selected. Caution: Never power the device without keeping the RSTIN pin grounded: The device could enter into unpredictable states, risking also permanent damage. ...

Page 80

... PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ 1ms (for on-chip VREG stabilization) ≤2 TCL ... ≥ ≤ 500 ns 3..4 TCL Transparent Not t. Transparent Not transparent ≤ 1ms Latching point of port0 for system start-up configuration ST10F272M Not t. Not t. Not t. 7 TCL ...

Page 81

... ST10F272M Figure 18. Asynchronous power-on reset ( XTAL1 RPD RSTIN RSTF (after filter) P0[15:13] P0[12:2] P0[1:0] ALE RST TCL depending on clock source selection Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in the reset circuitry chapter and in figures 30, 32 ...

Page 82

... Longer than 500 ns to take account of input filter on RSTIN pin. 82/176 (1) ≥ ≤ 500 ns ≥ ≤ 500 ns Transparent Not transparent Not transparent Transparent Not transparent system start-up configuration ST10F272M ≤ 2 TCL 3..4 TCL Not t. Not t. Not t. Not t. 7 TCL ≤ 1ms Latching point of port0 for ...

Page 83

... Flash is used, the restarting occurs after the embedded Flash initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 84

... Flash initialization when (internal memory selected). Then, the code execution restarts. The system configuration is latched from port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 85

... ST10F272M Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (approximately 2.5 V), the reset event becomes immediately asynchronous ...

Page 86

... Not transparent Not t. Transparent Not transparent 1024 TCL 8 TCL 200 µA discharge Section 21.1 Section 21.1). ST10F272M Not t. Not t. (3) 3..8 TCL 8 TCL At this time RSTF is sampled HIGH or LOW SHORT or LONG reset (2) V > 2.5 V asynchronous reset not entered RPD ...

Page 87

... ST10F272M Figure 23. Synchronous long hardware reset ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (after filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5V operation), the asynchronous reset is then immediately entered ...

Page 88

... Transparent Not transparent 1024+8 TCL At this time RSTF is sampled LOW LONG reset 200 µA discharge Section 21.1). 25 and 26 for unidirectional SW reset timing, and to figures 27, ST10F272M 3..4 TCL Not t. Not t. Not t. (3) 3..8 TCL 8 TCL (1) V > 2.5 V asynchronous reset not entered RPD ...

Page 89

... ST10F272M 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY READY is sampled active (low) after the programmed wait states ...

Page 90

... On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. 90/176 Not transparent Not t. Transparent Not transparent Not transparent Not t. 1024 TCL Figure 21 Figure 27 and Figure ST10F272M 8 TCL and 28), the software ...

Page 91

... ST10F272M The bidirectional reset is not effective in case RPD is held low, when a software or watchdog reset event occurs. On the contrary software or watchdog bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). ...

Page 92

... Not transparent ≤ 1ms 1024 TCL ≥ ≤ 500 ns Not transparent Transparent Not transparent Not transparent 1024 TCL ≥ Not t. Not t. ≤2 TCL 7 TCL ≥ ≤ 500 ns Not t. Not t. 8 TCL At this time RSTF is sampled HIGH WDT reset is flagged in WDTCON ST10F272M ...

Page 93

... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F272M is to insert a capacitor C1 between RSTIN pin and V , and a capacitor between RPD pin and V ...

Page 94

... This mechanism insures recovery from catastrophic failure. Figure 30. Minimum external reset circuitry The minimum reset circuit of the ST10F272M itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V reset sequence, and thus will trigger an asynchronous reset sequence. Figure 31 shows an example of a reset circuit ...

Page 95

... ST10F272M Figure 31. System reset circuit ST10F272M Figure 32. Internal (simplified) reset circuitry Internal reset signal External hardware RSTIN o.d. R0 Open drain inverter RPD + C0 EINIT instruction Clr Q Set Reset state machine clock SRST instruction Trigger watchdog overflow Clr Reset sequence (512 CPU clock cycles) ...

Page 96

... Reset application examples The next two timing diagrams bidirectional internal reset events (software and watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). 96/176 (Figure 33 and Figure 34) provide additional examples of ST10F272M Figure 31 for the ...

Page 97

... ST10F272M Figure 33. Example of software or watchdog bidirectional reset ( System reset 97/176 ...

Page 98

... System reset Figure 34. Example of software or watchdog bidirectional reset ( 98/176 ST10F272M ...

Page 99

... ST10F272M 20.9 Reset summary The following table summarizes the different reset events. Table 42. Reset event Event Asynch. Power-on reset Asynch Asynch Asynch. Hardware reset (asynchronous Asynch Asynch Synch Synch. Short hardware reset Synch. (1) (synchronous Synch Synch Synch. Long hardware reset Synch. ...

Page 100

... Asynchronous hardware reset Asynchronous power-on reset 100/176 RSTIN Min Not activated Not activated Not activated Activated by internal logic for 1024 TCL Not activated Not activated Not activated Activated by internal logic for 1024 TCL - - - ST10F272M WDTCON flags Max Section 20.3 for details). Figure 35 Port0 ...

Page 101

... ST10F272M Figure 35. Port0 bits latched into the different registers after reset H.7 H.6 H.5 H.4 H.3 CLKCFG SALSEL RP0H CLKCFG SALSEL Clock Port 4 generator logic P0L.7 ROMEN BYTDIS WRCFG Port0 H.2 H.1 H.0 L.7 L.6 L.5 CSSEL WRC BUSTYP CSSEL WRC ...

Page 102

... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F272M. In idle mode only CPU is stopped, while peripheral still operates. In power-down mode both CPU and peripherals are stopped. In stand-by mode the main power supply (V ...

Page 103

... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1. stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16 Kbytes for ST10F272M), the RTC counters and 32 kHz on-chip oscillator amplifier. Chapter 20: System reset on page ...

Page 104

... V 18SB from ST10F272M core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism ...

Page 105

... ST10F272M Warning: 21.3.2 Exiting stand-by mode After the system has entered the stand-by mode, the procedure to exit this mode consists of a standard power-on sequence, with the only difference that the RAM is already powered through V internal reference (derived from V 18SB It is recommended to held the device under reset (RSTIN pin forced low) until external V voltage pin is stable ...

Page 106

... Off On Off On Off Off Off Off On Off Off On On Off Off On On Off Off Off On Off Off On ST10F272M Table 44. Run Off Biased Biased Run On Biased Biased Off Off Biased Biased On Off Biased Biased Off On Biased Biased Off Off Biased Off Off ...

Page 107

... ST10F272M 22 Programmable output clock divider A specific register mapped on the XBUS can be used to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON possible to program the clock prescaling factor ...

Page 108

... Special function registers Table 45 lists all SFRs which are implemented in the ST10F272M in alphabetical order. Bit-addressable SFRs are marked with the letter ‘b’ in the column ‘Name’. SFRs within the extended sfr-space (ESFRs) are marked with the letter ‘E’ in the ‘Physical address’ ...

Page 109

... ST10F272M Table 45. List of special function registers (continued) Physical Name address CC4IC b FF80h CC5 FE8Ah CC5IC b FF82h CC6 FE8Ch CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 ...

Page 110

... CPU context pointer register B5h GPT2 CAPREL interrupt control register 04h CPU code segment pointer register (read only) E 80h P0L direction control register E 81h P0h direction control register ST10F272M Description Reset value - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h ...

Page 111

... ST10F272M Table 45. List of special function registers (continued) Physical Name address DP1L b F104h DP1H b F106h DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 b FFD6h DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h EMUCON FE0Ah EXICON b F1C0h EXISEL b F1DAh IDCHIP ...

Page 112

... PWM module up/down counter 1 E 1Ah PWM module up/down counter 2 E 1Bh PWM module up/down counter 3 18h PWM module pulse width register 0 19h PWM module pulse width register 1 ST10F272M Description Reset value - - 00h FFFFh - - 00h - - 00h - - 00h - - 00h 0000h 0000h ...

Page 113

... ST10F272M Table 45. List of special function registers (continued) Physical Name address PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh QR0 F004h QR1 F006h QX0 F000h QX1 F002h RP0H b F108h S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC b FF6Eh S0TBIC ...

Page 114

... E C7h See Section 9.1 E CBh See Section 9.1 E CFh See Section 9.1 E 12h XPER configuration register 8Eh Constant value 0’s register (read only) ST10F272M Description Reset value - - 00h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h ...

Page 115

... The XPnIC interrupt control registers control interrupt requests from integrated X-bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-peripheral nodes. 23.2 X-registers The following table lists all X-bus registers which are implemented in the ST10F272M ordered by their name. Note: The X-Registers are not bit-addressable. Table 46. ...

Page 116

... CAN2: IF1 message control CAN2: IF2 arbitration 1 CAN2: IF2 arbitration 2 CAN2: IF2 command mask CAN2: IF2 command request CAN2: IF2 data A 1 CAN2: IF2 data A 2 CAN2: IF2 data B 1 CAN2: IF2 data B 2 ST10F272M Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 117

... ST10F272M Table 46. List of X-bus registers (continued) Name Physical address CAN2IF2M1 EE44h CAN2IF2M2 EE46h CAN2IF2MC EE4Ch CAN2IP1 EEA0h CAN2IP2 EEA2h CAN2IR EE08h CAN2MV1 EEB0h CAN2MV2 EEB2h CAN2ND1 EE90h CAN2ND2 EE92h CAN2SR EE02h CAN2TR EE0Ah CAN2TR1 EE80h CAN2TR2 EE82h I2CCCR1 EA06h I2CCCR2 EA0Eh ...

Page 118

... XPWM module pulse width register 3 XPWM module control register 0 XPWM module clear control reg. 0 (write only) XPWM module set control register 0 (write only) XPWM module control register 1 XPWM module clear control reg. 0 (write only) ST10F272M Reset value XXXXh 0000h 0000h 0000h ...

Page 119

... ST10F272M Table 46. List of X-bus registers (continued) Name Physical address XPWMCON1SET EC0Ah XPWMPORT EC80h XS1BG E906h XS1CON E900h XS1CONCLR E904h XS1CONSET E902h XS1PORT E980h XS1RBUF E90Ah XS1TBUF E908h XSSCBR E80Ah XSSCCON E800h XSSCCONCLR E804h XSSCCONSET E802h XSSCPORT E880h XSSCRB E808h XSSCTB E806h ...

Page 120

... Flash registers ordered by name The following table lists all Flash control registers which are implemented in the ST10F272M ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on X-bus. Note that these registers are not bit-addressable. ...

Page 121

... ST10F272M 23.4 Identification registers The ST10F272M has four identification registers, mapped in ESFR space. These registers contain: ● A manufacturer identifier ● A chip identifier with its revision ● An internal Flash and size identifier ● Programming voltage description IDMANUF (F07Eh / 3Fh Table 48. IDMANUF register description ...

Page 122

... ESFR Internal memory size Internal memory size (MEMSIZE) (in Kbyte) 040h for 256 Kbytes (ST10F272M) Internal memory type 0h: ROM-Less 1h: (M) ROM memory 2h: (S) Standard Flash memory (ST10F272M) 3h: (H) High performance Flash memory 4h...Fh: Reserved ESFR PROGVPP RO voltage (no need of external V PP Programming V ...

Page 123

... ST10F272M 24 Electrical characteristics 24.1 Absolute maximum ratings Table 52. Absolute maximum ratings Symbol V Voltage Voltage on V STBY V Voltage on V AREF V Voltage on V AGND V Voltage on any pin with respect to ground ( Input current on any pin during overload condition OV I Absolute sum of all input currents during overload condition ...

Page 124

... Watts. This is the chip internal power DD DD < P and may be neglected. On the other hand, P I/O INT and ( Using this value of K, the values Value Min Max 4.5 5.5 ( 0.1 DD +125 -40 +150 voltage is lower STBY Section 24.7. ) may be I/O ( neglected) is given by: J I/O ST10F272M Unit V °C DD and ...

Page 125

... Where the external system must provide signals with their respective timing characteristics to the ST10F272M, the symbol ‘SR’ for system requirement, is included in the ‘Symbol’ column. Description Ambient temperature range -40 to +125° ...

Page 126

... I – V 0.05 I 0.4 I OL1 – V 0.05 I OL1 OL2 – 0 OL2 0 OL2 - 0 – 0. ST10F272M – – – – – – – – (1) (1) (1) (1) ( µ µ µA = – 8mA = – 1mA ...

Page 127

... ST10F272M Table 56. DC characteristics (continued) Parameter (2) Output high voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD (3) Input leakage current (P5[15:0]) Input leakage current (all except P5[15:0], P2[0], RPD, P3[12], P3[15]) (4) Input leakage current (P2[0]) Input leakage current (RPD) ...

Page 128

... – 120 µ – 500 µ – 2.5 mA Figure 37 for a scheme of the input is expressed in MHz). This dependency is is expressed in MHz). This dependency is ST10F272M ° 5.5 V STBY = ° 5.5 V STBY = T = 125 ° 5.5 V STBY = ° 5.5 V STBY = T = 125 °C J – ...

Page 129

... ST10F272M Figure 37. Port2 test mode structure Figure 38. Supply current versus the operating frequency (run and idle modes) 150 100 Clock Input Alternate data input latch Fast external interrupt input Test mode Flash sense amplifier and column decoder [MHz] CPU Electrical characteristics P2 ...

Page 130

... Absolute value of a word or double word programming time could be longer than the average value. 3. Bank erase is obtained through a multiple sector erase operation (setting bits related to all sectors of the bank). As ST10F272M implements only one bank, the bank erase operation is equivalent to module and chip erase operations. 4. Not 100% tested, guaranteed by design characterization. ...

Page 131

... ST10F272M Table 58. Flash data retention characteristics Number of program/erase cycles (-40 °C < 100 1000 10000 100000 1. Two 64 Kbyte Flash sectors may be typically used to emulate Kbytes of EEPROM. Therefore, in case of an emulation Kbyte EEPROM, 100,000 Flash program/erase cycles are equivalent to 800,000 EEPROM Program/Erase cycles. For an efficient use of the EEPROM emulation ...

Page 132

... The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F272M relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjustment of the ST10F272M A/D converter to the system’ ...

Page 133

... ST10F272M Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum ...

Page 134

... combination of the offset, gain and integral linearity errors. The different errors may compensate each other depending on the relative sign of the offset and gain errors. Refer to Figure 134/176 Figure 39): 39, see TUE. ST10F272M Figure 39. (Figure 39, see ...

Page 135

... ST10F272M Figure 39. A/D conversion characteristics 3FF 3FE 3FD 3FC 3FB 3FA Digital out (HEX) 007 006 005 004 003 002 001 000 Offset error OFS 24.7.4 Analog reference pins The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion ...

Page 136

... Pin capacitance (two contributions Sampling capacitance S 126. Input leakage is greatest at high operating temperatures, and substantially a switched capacitance, with a frequency S equal to 4 pF, a resistance of 1 MΩ where f represents the conversion rate at the considered ST10F272M Internal circuit scheme V DD Channel Sampling selection and ...

Page 137

... ST10F272M (sampled voltage on C must be designed to respect the following relation: The formula above provides constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network must be considered. Assuming the three capacitances equivalent circuit shown in close), a charge sharing phenomena is installed. ...

Page 138

... Being C F (at the end of the A2 . The following equation must be A1 already charged ⋅ ⋅ the filter is very high with longer than the sampling time C ≤ (conversion rate vs. filter pole (Anti-aliasing filtering condition ≤ f (Nyquist conversion rate ST10F272M P2 F must the S f ...

Page 139

... ST10F272M The considerations above imposes new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on C above simple to derive the following relation between the ideal and real sampled voltage From this formula, in the worst case (when V assuming to accept a maximum error of half a count (~2.44 mV), a constraint is immediately ...

Page 140

... V The other condition to be verified is if the time constants of the transients are really and significantly shorter than the sampling period duration T For the complete set of parameters characterizing the ST10F272M A/D converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page ...

Page 141

... It begins to float when a 100 mV change from the loaded V 24.8.2 Definition of internal timing The internal operation of the ST10F272M is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example, pipeline) or external (for example, bus cycles) operations. The specification of the external timing (AC characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called ‘ ...

Page 142

... CPU XTAL MHz XTAL 5 MHz XTAL MHz XTAL 6 MHz XTAL MHz XTAL MHz XTAL MHz XTAL - - ST10F272M TCLTCL TCLTCL TCL TCL Notes (1)(3) Default configuration Direct drive (oscillator bypassed) (3) CPU clock via prescaler Reserved /2, an external crystal or resonator XTAL (2) ...

Page 143

... If bit OWDDIS is set, then the PLL is switched off. 24.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F272M. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...

Page 144

... PLL jitter is negligible. Refer to next 144/176 the PLL circuit synchronizes the CPU clock to XTAL . The relative deviation of TCL is the maximum when it is referred to XTAL Section 24.8.9: PLL jitter ST10F272M Table 61). The PLL multiplies the input is constantly adjusted CPU which also effects the duration of CPU for more details ...

Page 145

... ST10F272M 24.8.8 Voltage controlled oscillator The ST10F272M implements a PLL which combines different levels of frequency dividers with a voltage controlled oscillator (VCO) working as frequency multiplier. The following table gives a detailed summary of the internal settings and VCO frequency. Table 62. Internal PLL divider mechanism P0.15-13 XTAL frequency (P0H ...

Page 146

... Lastly, for N greater than a second value saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods N). The PLL loop acts as a high pass filter for any 146/176 ST10F272M and T , where max ...

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... Its effects are strongly reduced thanks to the particular care used in the physical implementation and integration of the PLL module inside the device. Nonetheless, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure 46. ST10F272M PLL jitter ± 5 ± 4 ± 3 ± ...

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... Value Min Typ Max 1.4 2.6 4.2 – 1.5 – 0.8 – 6 – 1 ST10F272M Resonator ST10F272M Unit Max 300 µs 250 µs +500 ps 2000 kHz 4000 Unit mA/V – V – ...

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... -40 to +125 ° Parameter Conditions Startup (1) Normal run (2) Peak to peak (2) Sine wave middle (2) Stable V DD ST10F272M Crystal C A Electrical characteristics Typ Max Min Typ 430 Ω 850 Ω – 120 Ω 250 Ω – ...

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... IL2 150 kΩ 120 kΩ ) and the package capacitance 0 Direct drive with PLL usage prescaler CPU XTAL CPU XTAL Min Max Min 83.3 250 83.3 3 – – 6 – 2 – – 2 – and V . IH2 ST10F272M kΩ Unit Max 250 ns – ns – ...

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... ST10F272M Figure 49. External clock drive XTAL1 Note: When direct drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: When 40 MHz is used, 50% duty cycle is granted (low phase = high phase = 12.5 ns); when for instance 20 MHz is used duty cycle can be accepted (minimum phase, high or low, again equal to 12 ...

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... C 3TCL – 9 – C – 2TCL – – 3TCL – – 3TCL – 4TCL – – – – 2TCL – 8 2TCL – – C 2TCL – 8 – F 2TCL – – F 2TCL – – F – 4 – – – 3TCL - 3TCL - 10 – F ST10F272M Unit ...

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... ST10F272M Table 70. Multiplexed bus timings (continued) Symbol Parameter ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS WrCS (with RW delay)1 Address float after RdCS WrCS (no RW delay)1 RdCS to valid data (with RW delay) ...

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... Electrical characteristics Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE CLKOUT ALE CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH 154/176 Address Address Address ST10F272M Data in Address Data out ...

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... ST10F272M Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH Address t 7 Address Address Electrical characteristics t 25 ...

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... Electrical characteristics Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx 156/176 Address Address Address ST10F272M Address Data Data out ...

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... ST10F272M Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/data bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx Address t 7 Address Address Electrical characteristics Data Data out t 56 ...

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... TCL = MHz Min Max TCL - 8 – A TCL - – A 2TCL - 12 – A TCL - – A 2TCL - 9 – C 3TCL - 9 – C – 2TCL - – 3TCL - – 3TCL - – 4TCL - – – 2TCL - 8 – TCL - 8 2TCL - – C TCL - 8 – – – – – 3TCL - ST10F272M Unit ...

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... ST10F272M Table 71. Demultiplexed bus timings (continued) Symbol Parameter Latched CS hold after RD Address setup to RdCS WrCS 82 (with RW-delay) Address setup to RdCS WrCS 83 (no RW-delay) RdCS to valid data (with RW-delay) RdCS to valid data (no RW-delay) RdCS, WrCS low time (with RW-delay) RdCS, WrCS low time ...

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... Electrical characteristics Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 160/176 Address Data out ST10F272M 41u t ( 28h t 18 Data ...

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... ST10F272M Figure 55. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE CLKOUT ALE t CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH Address Electrical characteristics Data Data out 161/176 ...

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... Electrical characteristics Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 162/176 Address Data out ST10F272M Data ...

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... ST10F272M Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx Address Electrical characteristics Data Data out 163/176 ...

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... MHz Variable CPU clock 1/2 TCL = MHz Max Min Max 25 2TCL 2TCL – TCL - 3.5 – TCL - 2.5 4 – 4 – – 17 – 2 – 2TCL + 10 – 17 – refers to the current bus cycle. F ST10F272M Unit ns – ns – – ns – ns – ns – ns – ...

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... ST10F272M Figure 58. CLKOUT and READY CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 1. Cycle as programmed, including MCTC wait states (example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...

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... Figure 59. External bus arbitration (releasing the bus) CLKOUT HOLD HLDA BREQ CSx (P6.x) Others 1. The ST10F272M will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t 166/176 = -40 to +125 ° ...

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... This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain- sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F272M requesting the bus. 2. The next ST10F272M driven bus cycle may start here. ...

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... Variable baudrate (<SSCBR> = 0001h - FFFFh) Max Min Max – 2TCL + 12.5 – 4TCL – 2TCL – 125 ns (corresponding to 8 Mbaud). 300 (2) t 305 Last out bit t t 307 308 Last in bit ST10F272M Unit – ns – ns – ns – ns ...

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... ST10F272M 24.8.20.2 Slave mode ± Table 75. SSC slave mode timings Symbol Parameter ( SSC clock cycle time 310 t SR SSC clock high time 311 t SR SSC clock low time 312 t SR SSC clock rise time 313 t SR SSC clock fall time 314 ...

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... The bit timing is repeated for all bits to be transmitted or received. 170/176 310 311 312 t t 314 313 t t 315 316 315 1st out bit 2nd out bit t t 317 318 1st in bit 2nd in bit ST10F272M (2) t 315 Last out bit t t 317 318 Last in bit ...

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... ST10F272M 25 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

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... ST10F272M 0.10mm .004 Seating Plane C K inches Min Typ Max 0.1602 0.0098 0.1248 0.1346 0.1445 0.0087 0.0150 0.0051 ...

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... ST10F272M Figure 64. LQFP144 package dimension Note 1: Exact shape of each corner is optional. Table 77. LQFP144 mechanical data Dim Min Typ Max 1.600 0.050 0.150 1.350 1.400 1.450 0.170 0.220 0.270 0.090 0.200 22.000 20.000 17.500 0.500 22.000 20.000 17.500 0.450 0.600 0.750 1.000 3.5° ...

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... Ordering information 26 Ordering information Table 78. Device summary Order code ST10F272M-4Q3 ST10F272M-4QR3 ST10F272M-4T3 ST10F272M-4TR3 174/176 Package Packing Tray PQFP144 Tape and reel Tray LQFP144 Tape and reel ST10F272M Temperature CPU frequency range (°C) range (MHz) -40 to +125 ...

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... ST10F272M 27 Revision history Table 79. Document revision history Date Revision 09-May-2007 04-Jan-2008 1 Initial release Changed document status from Preliminary Data to Memory organization on page 4Kbytes Table 2: Summary of IFlash address range on page B0TF from 8 to 4Kbytes Figure 5: Flash structure on page 4Kbytes Table 5: Flash modules sectorization (write operations or with ROMS1 = ‘ ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 176/176 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST10F272M ...