ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet

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... Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power down and standby modes ■ Single voltage supply ±10% (embedded regulator for 1.8V core supply) ■ Temperature range: -40 / +125 °C Rev 2 ST10F273M LQFP144 ( 1.4mm) (Low Profile Quad Flat Package) 1/182 www.st.com 1 ...

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... Flash data register 0 low (FDR0L Flash data register 0 high (FDR0H Flash data register 1 low (FDR1L Flash data register 1 high (FDR1H Flash address register low (FARL Flash address register high (FARH Flash error register (FER XFlash interface control dummy register (XFICR Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ST10F273M ...

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... ST10F273M 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 48 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3 Alternate and selective boot mode (ABM and SBM ...

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... CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.2.1 17.2.2 17.2.3 18 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20.3 Synchronous reset (warm reset 4/182 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ST10F273M ...

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... ST10F273M 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 21.2.1 21.2.2 21.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21 ...

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... Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Oscillator watchdog (OWD 149 Phase locked loop (PLL 150 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 ST10F273M ...

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... Table 23. FNVAPR1L register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 24. FNVAPR1H register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 25. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 26. Flash write operations Table 27. ST10F273M boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 28. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 29. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 31. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 32. ...

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... Table 73. CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 74. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 75. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 76. SSC slave mode timings 175 Table 77. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 78. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8/182 = 5V ± ST10F273M = -40°C to +125° 153 ...

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... List of figures Figure 1. ST10F273M Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Pin configuration (top view Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. ST10F273M memory mapping (XADRS3 = 800Bh - reset value Figure 5. ST10F273M memory mapping (XADRS3 = E009h - user programmed value Figure 6. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7. Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. CPU block diagram (MAC unit not included Figure 9 ...

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... External bus arbitration (releasing the bus 172 Figure 61. External bus arbitration (regaining the bus 173 Figure 62. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 63. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 64. PQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 65. LQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10/182 ST10F273M ...

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... Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F273M is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V. ...

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... Introduction Figure 1. ST10F273M Logic symbol 12/182 XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F273M NMI STBY READY ALE WRL Port 5 16-bit ST10F273M Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD ...

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... P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 ST10F273M Pin data 108 P0H.0 / AD8 107 P0L.7 / AD7 106 P0L.6 / AD6 105 P0L.5 / AD5 104 P0L.4 / AD4 103 P0L ...

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... CAPCOM2: CC20 capture input / compare output P8.5 CC21IO CAPCOM2: CC21 capture input / compare output P8.6 CC22IO CAPCOM2: CC22 capture input / compare output RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous) P8.7 CC23IO CAPCOM2: CC23 capture input / compare output TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous) ST10F273M Function ...

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... ST10F273M Table 1. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5. 47-54 I/O 57-64 47 I/O ... ... P2.0 - P2.7 54 I/O P2.8 - P2.15 I ... ... I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state ...

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... ASC0: data input (asynchronous) or I/O (synchronous) BHE External memory high byte enable signal P3.12 WRH External memory high byte write strobe P3.13 SCLK0 SSC0: master clock output / slave clock input System clock output (programmable divider on CPU P3.15 CLKOUT clock) ST10F273M Function ...

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... ST10F273M Table 1. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 WR/WRL 96 O READY READY ALE 98 O Port 8-bit bidirectional I/O port bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS) ...

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... I 18/182 External access enable pin. A low level applied to this pin during and after Reset forces the ST10F273M to start the program from the external memory space. A high level forces ST10F273M to start in the internal memory space. This pin is also used (when Standby mode is entered, that is ST10F273M under reset and main V ...

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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F273M to go into power down mode. If NMI is high and PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in normal mode ...

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... Functional description 3 Functional description The architecture of the ST10F273M combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F273M. Figure 3. Block diagram XRAM1 ...

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... B1F0 / B0F10 B1F1 / B0F11 Note: A single Flash bank is implemented on the ST10F273M compared to the ST10F273E. The last two sectors (B0F10 and B0F11) can be seen as the Bank1 of the ST10F273E in order to maintain the compatibility with the existing Flash programming drivers. For this, the control and status bit of the blocks B0F10 and B0F11 have been duplicated to be usable as blocks B1F0 and B1F1 of the ST10F273E. XFLASH / Flash Control Registers: Address range 0E’ ...

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... RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. 22/182 is turned off. ST10F273M pin when the STBY ...

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... Mbytes of external memory can be connected to the microcontroller. Visibility of XBUS peripherals In order to keep the ST10F273M compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-Peripheral enabling in XPERCON register must be set. If these bits are cleared before the ...

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... XPERCON register are not be clocked. The clock gating can reduce power consumption and improve EMI when the user does not use all X-Peripherals. Note: When the clock has been gated in the disabled peripherals, no Reset will be raised once the EINIT instruction has been executed. 24/182 ST10F273M ...

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... ST10F273M Figure 4. ST10F273M memory mapping (XADRS3 = 800Bh - reset value) Code Data Code Segment Page Segment FF FFFF 1023 11 FFFF 255 17 11 0000 10 FFFF 16 10 0000 0F FFFF Reserved 15 XRAM2 (StandBy) 0F 0000 0E FFFF Flash 14 Control Registers 0E 0000 0D FFFF 13 B3F1 Reserved (XFLASH) 0D 0000 0C FFFF 12 Reserved ...

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... Memory organization Figure 5. ST10F273M memory mapping (XADRS3 = E009h - user programmed value) Code Data Code Segment Page Segment FF FFFF 1023 11 FFFF 255 17 11 0000 10 FFFF 16 10 0000 0F FFFF Reserved 15 XRAM2 (StandBy) 0F 0000 0E FFFF Flash 14 Control Registers 0E 0000 0D FFFF 13 0D 0000 0C FFFF 12 0C 0000 ...

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... ST10F273M 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed of one matrix module of one bank of 512 Kbytes, named Bank0, that can be read and modified. This module is called IFlash because the ST10 Internal bus. Figure 6. Flash structure The programming operations of the Flash are managed by an embedded Flash Program/Erase Controller (FPEC) ...

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... This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be accessible as blocks B1F0 and B1F1. 28/182 operations)), and when accessed in write Description (1) (1) ST10F273M Addresses Size (bytes) 0x00 0000 - 0x00 1FFF 0x00 2000 - 0x00 3FFF 0x00 4000 - 0x00 5FFF 0x00 6000 - 0x00 7FFF ...

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... ST10F273M Table 5. Flash module sectorization (write operations, or ROMS1 = ‘1’) Bank B0 Bank 0 Flash 10 (B0F10 / B1F0) Bank 0 Flash 11 (B0F11 / B1F1 single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E). ...

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... DFB0 - 0x0E DFB3 0x0E DFB8 - 0x0E DFB9 0x0E DFBC - 0x0E DFBF 0x0E E000 - 0x0E E001 ST10F273M Size Bus size 8 byte 8 byte 4 byte 2 byte 4 byte ...

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... replication of the BSY0 bit set whenever a write operation is on-going. This bit is emulating the BSY1 bit of the ST10F273E device. When write operations are on going on B0F10 and/or B0F11 blocks of the ST10F273M, this bit will be set in order to indicate that their equivalent B1F0 or B1F1 in the ST10F273E are busy ...

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... It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect. Function FCR Reset value: 0000h Reserved MOD RW - Function ST10F273M ...

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... DFBF. SPR bit is automatically reset at the end of the Set Protection operation. This is a dummy SMOD bit that is maintaining software compatibility with the ST10F273E where it must be set before every Write Operation to the IFlash. It has no effect in the ST10F273M. Internal Flash memory Function (1) ...

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... Write operation if no errors are detected. FCR DB1S B0S RS RS Reset value: 0000h B0F B0F B0F B0F B0F Function meaning. These bits are Reset value: 0000h Reserved - ST10F273M 1 0 B0F B0F Table 11 B0F11 B0F10 /B1F1 /B1F0 RS RS ...

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... ST10F273M Table 10. FCR1H register description Bit Name 15: DB1S 8 B0S 7:2 - B0F10/B1F0 1:0 B0F11/B1F1 Table 11. Bank (BxS) and sectors (BxFy) status bits meaning Operation Erase Suspend 5.4.5 Flash data register 0 low (FDR0L) During program operations, the Flash Address Registers (FARH/L) are used to store the Flash address in which to program and the Flash Data Registers (FDR1H/L-FDR0H/L) are used to store the Flash data to program ...

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... Data input 31:16 These bits must be written with the Data to program in Flash during the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection. Function Reset value: FFFFh DIN DIN DIN DIN DIN DIN Function ST10F273M 1 0 DIN DIN ...

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... ST10F273M 5.4.7 Flash data register 1 low (FDR1L) FDR1L (0x0E 000C DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 Table 14. FDR1L register description Bit Name Data input 15:0 15:0 DIN[15:0] 5.4.8 Flash data register 1 high (FDR1H) ...

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... This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid Write Operation. In this case no Write Operation is executed. This bit must be cleared by software. Reserved. These bits must be kept to their default value (0). ST10F273M Reset value: 0000h ...

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... Dummy Wait States 3:0 In the ST10F273E, these bits were used to configure the number of wait- states to access the XFlash. As there is no XFlash on the ST10F273M, these bits have no effect. This register is implemented for software compatibility with the ST10F273E. Reserved. These bits must be kept to their default value (0). ...

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... B0F11 and B0F10). After a protection command, these bits will reflect the value of bit 0 and 1 of FVWPIRH register (W0P11 and W0P10). Write protection bank 0 / sectors 9-0 These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFlash). ST10F273M Section 5.4: Delivery value: FFFFh ...

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... ST10F273M 5.5.3 Flash non-volatile write protection I register high (FNVWPIRH) FNVWPIRH (0x0E DFB6 Table 21. FNVWPRIH register bits Bit Name 15:2 - W0P11/W1P1 1:0 W0P10/W1P0 5.5.4 Flash non-volatile write protection I register low Mirror (FNVWPIRL-m) FNVWPIRL-m (0x0E DFB0 Reserved - This register is mirroring the register at FVWPIRL (address 0x0E DFB4 intended to maintain software compatibility with the ST10F273E ...

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... ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. Delivery value: ACFFh Description Delivery value: FFFFh PDS PDS PDS PDS PDS Function ST10F273M 1 0 DBGP ACCP PDS PDS ...

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... ST10F273M 5.5.8 Flash non-volatile access protection register 1 high (FNVAPR1H) FNVAPR1H (0x0E DFBE PEN1 PEN1 PEN1 Table 24. FNVAPR1H register bits Bit Name Protections enable 15-0 PEN15 15:0 ... PEN0 5.5.9 Access protection The IFlash module has one level of access protection (access to data both in Reading and ...

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... Read XRAM or Read IFlash / external memory / Jump to IFlash Jump to XRAM or external memory No / Yes Yes / Yes No / Yes Yes / Yes /*Set WPG in FCR0H*/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ ST10F273M Read Flash Write Flash registers registers Yes No Yes No ...

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... ST10F273M FCR0H|= 0x8000; Double word program Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and data 0xAA55AA55 at address 0x03555C. FCR0H |= 0x1000; FARL = 0x5558; FARH = 0x0003; FDR0L = 0x55AA; FDR0H = 0x55AA; FDR1L = 0xAA55; FDR1H = 0xAA55; FCR0H |= 0x8000; Double Word Program is always performed on the Double Word aligned on an even Word: bit ADD2 of FARL is ignored ...

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... SPR in FCR0H*/ /*Set SPR in FCR0H*/ = 0xDFBC; /*Load Add of register FNVAPR1L in FARL*/ = 0x000E; /*Load Add of register FNVAPR1L in FARH*/ = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ /*Operation start*/ /*Load Add register FNVAPR1H in FARL*/ = 0x000E; /*Load Add register FNVAPR1H in FARH*/ /*Operation start*/ ST10F273M ...

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... ST10F273M 5.7 Write operation summary In general, each write operation is started through a sequence of three steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. 2. The second step is the definition of the Address and Data for programming or the sectors to erase ...

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... Standard bootstrap loader After entering the standard BSL mode and the respective initialization, the ST10F273M scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line. Start condition on UART RxD: ST10F273M starts standard bootstrap loader. This bootstrap loader is identical to that of other ST10 devices (example: ST10F269, ST10F168) ...

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... ST10F273M 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The behavior of the Selective Boot mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature ...

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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F273M’s instructions can be executed in one instruction cycle which requires 50ns at 40 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...

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... ST10F273M 7.1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with operands per instruction cycle. ...

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... Central processing unit (CPU) 7.2 Instruction set summary Table 28 lists the instructions of the ST10F273M. The detailed description of each instruction can be found in the ST10 Family Programming Manual. Table 28. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) ...

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... ST10F273M Table 28. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if direct bit is (not) set ...

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... Central processing unit (CPU) 7.3 MAC co-processor specific instructions Table 29 lists the MAC instructions of the ST10F273M. The detailed description of each instruction can be found in the ST10 Family Programming Manual. Note that all MAC instructions are encoded on 4 bytes. Table 29. MAC instruction set summary ...

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... ST10F273M 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different external memory access modes: ● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed ● ...

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... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F273M has eight PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...

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... ST10F273M Table 30. Interrupt sources (continued) Source of interrupt or PEC service request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 ...

Page 58

... XP2IE XP2INT XP3IR XP3IE XP3INT 2 C, PWM1 and RTC need some resources to implement interrupt Figure 10, the principle is explained through a simple XIRxSEL[15:8] Interrupt Enable bits XIRxSEL[7:0] Interrupt Flag bits ST10F273M Vector Trap location number 00’0098h 26h 00’009Ch 27h 00’00A0h 28h 00’00A4h 29h 00’ ...

Page 59

... ST10F273M available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also ...

Page 60

... BTRAP 00’0028h MACTRP BTRAP 00’0028h PRTFLT BTRAP 00’0028h ILLOPA BTRAP 00’0028h ILLINA BTRAP 00’0028h ILLBUS BTRAP 00’0028h [002Ch - 003Ch] Any 0000h – 01FCh in steps of 4h ST10F273M Trap Trap (1) number priority 00h III 00h III 00h III 02h II 04h II 06h II 0Ah I 0Ah ...

Page 61

... ST10F273M 10 Capture / compare (CAPCOM) units The ST10F273M has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 200ns at 40 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), digital to analog (D/A) conversion, software timing, or time recording relative to external events ...

Page 62

... MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 0.8µs 1.6µs 52.4ms 104.8ms 100b 101b 110b 128 256 512 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms ST10F273M 111b 1024 39.1 kHz 25.6µs 1.678s ...

Page 63

... ST10F273M 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...

Page 64

... T3IN T3EUD T4IN CPU clock T4EUD 64/182 n=3...10 mode Reload control Capture n 2 n=3...10 T3 mode control Capture Reload T4 mode control n 2 n=3...10 ST10F273M U/D Interrupt GPT1 timer T2 request T3OUT GPT1 timer T3 T3OTL U/D Interrupt request Interrupt GPT1 timer T4 request U/D ...

Page 65

... ST10F273M 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) ...

Page 66

... Figure 12. Block diagram of GPT2 T5EUD CPU clock 2 T5IN CAPIN T6IN CPU clock 2 T6EUD 66/182 n n=2...9 T5 GPT2 timer T5 mode control Clear Capture GPT2 CAPREL T6 GPT2 timer T6 mode n n=2...9 control ST10F273M U/D Interrupt request Interrupt request Reload Interrupt request Toggle FF T60TL T6OUT U/D to CAPCOM timers ...

Page 67

... ST10F273M 12 PWM modules Two pulse width modulation modules are available on ST10F273M: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or center-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. ...

Page 68

... I/O’s special features 13.2.1 Open drain mode Some of the I/O ports of ST10F273M support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections) and is controlled through the respective Open Drain Control Registers ODPx ...

Page 69

... ST10F273M 13.2.2 Input threshold control The standard inputs of the ST10F273M determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...

Page 70

... All port lines that are not used for these alternate functions may be used as general purpose I/O lines. 70/182 ST10F273M ...

Page 71

... The ST10F273M has multiplexed input channels on Port 5 and Port 1 respectively. The selection between Port 5 and Port 1 is made via a bit in an XBus register. Refer to the User Manual for a detailed description. ...

Page 72

... CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: The bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a conversion. 72/182 ST10F273M ...

Page 73

... SSC1 (XBUS mapped). 15.1 Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F273M and other microcontrollers, microprocessors or external peripherals. 15.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...

Page 74

... Serial channels 15.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F273M. Half-duplex communication Mbaud (at 40 MHz possible in this mode. CPU Table 39. ASC synchronous baudrates by reload value and deviation errors S0BRS = ‘0’, f CPU ...

Page 75

... ST10F273M Table 40. SSC synchronous baudrate and reload values Baudrate for f Reserved Can be used only with f 6.6 Mbaud 5 Mbaud 2.5 Mbaud 1 Mbaud 100 Kbaud 10 Kbaud 1 Kbaud 306 baud = 40 MHz CPU = 32 MHz (or lower) CPU Serial channels Bit time Reload value - 0000h - 0001h 150ns ...

Page 76

... C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I 2 Fast I C mode (100 to 400 kHz). 76/182 2 C Bus specification. The bus modes are supported interface can be selected between Standard mode (0 to 100 kHz) and ST10F273M 2 C Module can ...

Page 77

... XMISCEN of the XPERCON register and bit XPEN of the SYSCON register. 17.2 CAN bus configurations Depending on the application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F273M can support both configurations. 21. CAN modules 2 ...

Page 78

... Figure 14. Connection to single CAN bus via separate CAN transceivers CAN_H CAN_L The ST10F273M also supports single CAN bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment ...

Page 79

... ST10F273M 17.2.2 Multiple CAN bus The ST10F273M provides two CAN interfaces to support such kind of bus configuration as shown in Figure 16. Figure 16. Connection to two different CAN buses (for example for gateway application) CAN_H CAN_L 17.2.3 Parallel mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 17 ...

Page 80

... Vice versa, when at power on and after Reset, the 32 kHz is not present, the main STBY oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Standby mode, while in Power-down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled). 80/182 ST10F273M ...

Page 81

... ST10F273M 19 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. ...

Page 82

... Table Conditions Power-on (1) t > RSTIN t > (1032 + 12)TCL + max(4 TCL, 500ns) RSTIN t > max(4 TCL, 500ns) RSTIN ≤ (1032 + 12)TCL + max(4 TCL, 500ns) t RSTIN WDT overflow SRST instruction execution and 20.6 use the following ST10F273M 42. ...

Page 83

... ST10F273M does not need a stabilized clock signal to detect an asynchronous reset suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled ...

Page 84

... The internal 1.8V drivers are sized to drive currents of several tens of amps, so the current must be limited by the external hardware. The limit of current is imposed by power dissipation considerations (refer to Section 24: Electrical characteristics). 19 Asynchronous Power-on timing diagrams are shown, respectively with ST10F273M pin should not 18 and 18 ...

Page 85

... ST10F273M Figure 18. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3 ...

Page 86

... PLL stabilization) ≥ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) (1) 3..8 TCL ... ≥ ≤ 500 ns 3..4 TCL transparent transparent not transparent Latching point of Port0 for system start-up configuration ST10F273M not t. not t. not t. 8 TCL 32 and 33. ...

Page 87

... ST10F273M Figure 20. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than 500ns to take into account of Input Filter on RSTIN pin. 1) ≥ ≤ 500 ns ≥ ...

Page 88

... Flash is used, the restarting occurs after the embedded Flash initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F273M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 89

... Flash initialization when (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F273M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 90

... For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter). 90/182 24 and 25 report the timing of a Figure 20. There is no effect if RPD comes again above ST10F273M ...

Page 91

... ST10F273M Figure 22. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. RSTIN assertion can be released there. Refer also during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered ...

Page 92

... TCL 200µA Discharge Section 21.1 Section 21.1). ST10F273M not t. not t. 3..8 TCL3) 8 TCL 8 TCL At this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) VRPD > 2.5V Asynchronous Reset not entered for details on minimum pulse duration. ...

Page 93

... ST10F273M Figure 24. Synchronous long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered ...

Page 94

... TCL At this time RSTF is sampled LOW LONG reset 1) V 200µA Discharge RPD Section 21.1). ST10F273M 3..4 TCL not t. not t. not t. 3) 3..8 TCL 8 TCL > 2.5V Asynchronous reset not entered ...

Page 95

... ST10F273M Refer to the next Figures and 30 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY READY is sampled active (low) after the programmed wait states ...

Page 96

... TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to 96/182 not transparent transparent not transparent not transparent 1024 TCL Figure 28 and Figure ST10F273M not t. not t. 8 TCL Figure 22 and 29), the Software ...

Page 97

... ST10F273M or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL) ...

Page 98

... System reset Figure 28 WDT bidirectional RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT 98/182 ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL ST10F273M not t. not t. ≤ 2 TCL 7 TCL ...

Page 99

... ST10F273M Figure 29 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ≥ ≤ 500 ns not transparent transparent not transparent not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON System reset not t ...

Page 100

... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F273M is to insert a capacitor C1 between RSTIN pin and V , and a capacitor between RPD pin and V ...

Page 101

... This mechanism insures recovery from very catastrophic failure. Figure 31. Minimum external reset circuitry The minimum reset circuit of the ST10F273M itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V reset sequence, and thus will trigger an asynchronous reset sequence. Figure 32 shows an example of a reset circuit ...

Page 102

... EINIT Instruction Clr Q Set Reset state machine clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU clock cycles) Asynchronous Reset From/to exit power down circuit ST10F273M External reset source RSTOUT V DD BDRSTEN V DD Weak pull down (~200µA) RSTIN ...

Page 103

... ST10F273M 20.8 Reset application examples The next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 34. Example of software or watchdog bidirectional reset ( (Figure 34 and Figure 35) provide additional examples of ...

Page 104

... System reset Figure 35. Example of software or watchdog bidirectional reset ( 104/182 ST10F273M ...

Page 105

... ST10F273M 20.9 Reset summary The following table summarizes the different reset events. Table 43. Reset event Event Asynch. Power-on Reset Asynch Asynch Asynch. Hardware Reset (Asynchronous Asynch Asynch Synch Synch. Short Hardware Reset Synch. (1) (Synchronous Synch Synch Synch. Long Hardware Reset Synch. ...

Page 106

... Not activated Activated by internal logic for 1024 TCL Not activated Not activated Not activated Activated by internal logic for 1024 TCL Section 20.6 for details). and Figure 36. summarizes the state of bits of PORT0 latched in RP0H, SYSCON ST10F273M WDTCON flags Max Section 20.3 PORT0 ...

Page 107

... ST10F273M Figure 36. PORT0 bits latched into the different registers after reset H.7 H.6 H.5 H.4 H.3 CLKCFG SALSEL RP0H CLKCFG SALSEL Clock Port 4 Generator Logic P0L.7 P0L.7 ROMEN BYTDIS WRCFG PORT0 H.2 H.1 H.0 L.7 L.6 L.5 CSSEL WRC BUSTYP CSSEL ...

Page 108

... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F273M. In Idle mode only the CPU is stopped, while peripherals still operate. In Power-down mode both the CPU and peripherals are stopped. In Standby mode the main power supply (V ...

Page 109

... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Standby mode) to bias all those circuits that shall remain active: the portion of XRAM (16 Kbytes for ST10F273M), the RTC counters and 32 kHz on- chip oscillator amplifier. Section 20: System reset on page ...

Page 110

... V 18SB from ST10F273M Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism ...

Page 111

... ST10F273M Warning: 21.3.2 Exiting standby mode After the system has entered the Standby mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V internal reference (derived from V 18SB It is recommended to held the device under RESET (RSTIN pin forced low) until external V voltage pin is stable ...

Page 112

... Power reduction modes summary (continued) Mode on Power-down on on off Standby off 112/182 on off off off on off off on on off off on on off off off on off off on ST10F273M off off biased biased on off biased biased off on biased biased off off biased off off on biased off ...

Page 113

... ST10F273M 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON possible to program the clock prescaling factor: in this way on P3 ...

Page 114

... This section summarizes all registers implemented in the ST10F273M, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F273M in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 115

... ST10F273M Table 46. List of special function registers (continued) Physical Name address CC4 FE88h CC4IC b FF80h CC5 FE8Ah CC5IC b FF82h CC6 FE8Ch CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC ...

Page 116

... CAPCOM Mode Control register 6 94h CAPCOM Mode Control register 7 08h CPU Context Pointer register B5h GPT2 CAPREL interrupt control register 04h CPU Code Segment Pointer register (read only) 80h P0L direction control register ST10F273M Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...

Page 117

... ST10F273M Table 46. List of special function registers (continued) Physical Name address DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 b FFD6h DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h EMUCON FE0Ah EXICON b F1C0h E EXISEL ...

Page 118

... CPU program status word 18h PWM module up/down counter 0 19h PWM module up/down counter 1 1Ah PWM module up/down counter 2 1Bh PWM module up/down counter 3 18h PWM module pulse width register 0 ST10F273M Reset value - - 00h - - 00h FFFFh - - 00h - - 00h - - 00h - - 00h 0000h ...

Page 119

... ST10F273M Table 46. List of special function registers (continued) Physical Name address PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 F000h E QX1 F002h E RP0H b F108h E S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC ...

Page 120

... Watchdog timer control register 0Eh XPER address select register 3 C3h See Section 9.1 C7h See Section 9.1 CBh See Section 9.1 CFh See Section 9.1 ST10F273M Reset value 0000h - - 00h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h ...

Page 121

... X-registers The following table lists in order of their names all X-Bus registers which are implemented in the ST10F273M. Even though they are also physically mapped on XBus memory space, the Flash control registers are listed in a separate section. Note: The X-Registers are not bit-addressable. ...

Page 122

... CAN2: IF1 data B 1 EE24h CAN2: IF1 data B 2 EE14h CAN2: IF1 mask 1 EE16h CAN2: IF1 mask 2 EE1Ch CAN2: IF1 message control EE48h CAN2: IF2 arbitration 1 EE4Ah CAN2: IF2 arbitration 2 ST10F273M Reset value 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h ...

Page 123

... ST10F273M Table 47. List of XBus registers (continued) Name CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL RTCCON RTCDH RTCDL RTCH ...

Page 124

... XPWM module period register 3 EC10h XPWM module up/down counter 0 EC12h XPWM module up/down counter 1 EC14h XPWM module up/down counter 2 EC16h XPWM module up/down counter 3 EC30h XPWM module pulse width register 0 ST10F273M Reset value XXXXh XXXXh XXXXh - - 00h XXXXh XXXXh XXXXh XXXXh ...

Page 125

... ST10F273M Table 47. List of XBus registers (continued) Name XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB Physical Description address EC32h XPWM module pulse width register 1 EC34h ...

Page 126

... Register set 23.3 Flash registers ordered by name The following table lists in the order of their names all Flash Control Registers which are implemented in the ST10F273M. These registers are physically mapped on the XBus. Note: These registers are not bit-addressable. Table 48. List of Flash control registers ...

Page 127

... ST10F273M identifier (273) Xh: According to revision number ESFR Internal memory size Internal memory size (MEMSIZE) (in Kbyte) 080h for 512 Kbytes (ST10F273M) Internal memory type 0h: ROM-Less 1h: (M) ROM memory 2h: (S) Standard Flash memory (ST10F273M) 3h: (H) High performance Flash memory 4h...Fh: Reserved Reset value: 0403h ...

Page 128

... Note: All identification words are read-only registers. 128/182 ESFR PROGVPP RO voltage (no need of external V PP Programming V voltage DD V voltage when programming EPROM or Flash devices is calculated using DD the following formula [PROGVDD] / 256 (volts) - 40h for DD ST10F273M (5V). Reset value: 0040h PROGVDD RO Function ) - 00h PP ST10F273M 1 0 ...

Page 129

... ST10F273M 24 Electrical characteristics 24.1 Absolute maximum ratings Table 53. Absolute maximum ratings Symbol V Voltage Voltage on V STBY V Voltage on V AREF V Voltage on V AGND V Voltage on any pin with respect to ground ( Input current on any pin during overload condition OV I Absolute sum of all input currents during overload condition ...

Page 130

... On the other hand, I/O INT and 273°C) ( 273°C) + Θ Using this value of K, the values Value Min Max 4.5 5 0.1 DD +125 -40 +150 voltage is lower than main STBY power supply DD Section 24.7. x Θ neglected) is given by ST10F273M Unit V °C and ...

Page 131

... Where the ST10F273M logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the ST10F273M, the symbol “SR” for System Requirement, is included in the “Symbol” column. 24.5 DC characteristics ± ...

Page 132

... V = 60µA 0 -8mA V - 0.8 DD – = -1mA -4mA V - 0.8 DD – = -0.5mA -2mA 0 = -750µA 0.3 V – -150µA 0 – – ±0.2 – – ±0.5 +1.0 – – -0.5 – – ±3.0 ST10F273M Unit + µA µA µA µA ...

Page 133

... ST10F273M Table 57. DC characteristics (continued) Symbol | Input leakage current (P3[12], P3[15]) OZ5 | Overload current (all except P2[0]) OV1 | Overload current (P2[0]) OV2 R CC RSTIN pull-up resistor RST I Read/Write inactive current RWH I Read/Write active current RWL I ALE inactive current ALEL (4)(7) I ALE active current ...

Page 134

... IH1min IH1Min < –0.3 V). The absolute sum of input overload currents on all port pins OV Figure 38 for a scheme of the input is expressed in MHz). This dependency is and at maximum CPU clock frequency with all is expressed in MHz). This dependency is is expressed in MHz). This dependency is CPU ST10F273M DD DD ...

Page 135

... ST10F273M Figure 38. Port2 test mode structure Fast external interrupt input Figure 39. Supply current versus the operating frequency (RUN and IDLE modes Clock Input Alternate data input latch Test mode Flash sense amplifier and column decoder [MHz] CPU Electrical characteristics P2.0 CC0IO ...

Page 136

... The absolute value of a Word or Double Word Programming time could be longer than the average value. 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As ST10F273M implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations. 4. Not 100% tested, guaranteed by Design Characterization ...

Page 137

... ST10F273M Table 59. Flash data retention characteristics Number of program / erase cycles (-40°C < T < 125° 100 1000 10000 100000 1. Two 64 Kbyte Flash Sectors may be typically used to emulate Kbytes of EEPROM. Therefore, in case of an emulation Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM Program/Erase cycles. ...

Page 138

... The time that the two different actions (sampling, and converting) take during conversion can be programmed within a certain range in the ST10F273M relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent ...

Page 139

... ST10F273M from the general speed of the controller. This allows adjusting the A/D converter of the ST10F273M to the properties of the system: Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. ...

Page 140

... The number provided in the datasheet represents the maximum error with respect to the entire characteristic combination of the offset, gain and integral linearity errors. The different errors may compensate each other depending on the relative sign of the offset and gain errors. Refer to 140/182 Figure 40): ). Figure 40, see TUE. ST10F273M Figure 40. (Figure 40, see ...

Page 141

... ST10F273M Figure 40. A/D conversion characteristics 3FF 3FE 3FD 3FC 3FB 3FA Digital Out 007 (HEX) 006 005 004 003 002 001 000 1 Offset Error OFS 24.7.4 Analog reference pins The accuracy of the A/D converter depends on the accuracy of its analog reference: A noise in the reference results in at least that much error in a conversion ...

Page 142

... Input leakage is greatest at high operating temperatures = 50kΩ of external resistance leads being substantially a switched capacitance, with a frequency where f represents the conversion rate at the considered INTERNAL CIRCUIT SCHEME V DD Channel Sampling selection and Figure 41), in combination L equal to 4pF, a resistance of 1MΩ is ST10F273M 5V), AREF ...

Page 143

... ST10F273M (sampled voltage on C must be designed to respect the following relation: The formula above provides constraints for external network design, in particular on a resistive path. A second aspect involving the capacitance network must be considered. Assuming the three capacitances equivalent circuit reported in close), a charge-sharing phenomena is installed. ...

Page 144

... F (that is typically bigger than the on-chip ) constraint ≤ (filter resistance). C being F F (at the end of the charge A2 . The following equation must be A1 already charged ⋅ ⋅ the filter is very high with longer than the sampling time C = conversion rate ST10F273M P2 must the S f ...

Page 145

... ST10F273M The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on C above simple to derive the following relation between the ideal and real sampled voltage From this formula, in the worst case (when V assuming to accept a maximum error of half a count (~2.44mV), a constraint is immediately ...

Page 146

... V The other condition to be verified is if the time constants of the transients are really and significantly shorter than the sampling period duration T For the complete set of parameters characterizing the ST10F273M A/D converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page ...

Page 147

... It begins to float when a 100mV change from the loaded V 24.8.2 Definition of internal timing The internal operation of the ST10F273M is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “ ...

Page 148

... F CPU XTAL Main OSC (MHz XTAL 5.3 to 10.6 XTAL XTAL 6 XTAL XTAL XTAL XTAL - TCL TCL TCL TCL TCL TCL (1)(2) Notes Default configuration Direct drive (oscillator bypassed CPU clock via prescaler - Reserved /2, an external crystal or resonator XTAL ST10F273M (3) (2) ...

Page 149

... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 24.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F273M. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...

Page 150

... PLL jitter is negligible. Refer to the next details. 24.8.8 Voltage controlled oscillator The ST10F273M implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. page 151 gives a detailed summary of the internal settings and VCO frequency. ...

Page 151

... ST10F273M Table 63. Internal PLL divider mechanism P0.15-13 XTAL frequency (P0H.7- MHz 5.3 to 10.6 MHz MHz 6 MHz MHz MHz Reserved Note: The PLL input frequency range is limited 3.5 MHz, while the VCO oscillation range 128 MHz. The CPU clock frequency range when PLL is used MHz. ...

Page 152

... PLL module inside the device. Anyhow, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure 152/182 3 noise, the R.M.S. value of the accumulated jitter is proportional to N, 47. ST10F273M 3 . Assuming a noiseless 2 noise, the R.M.S. value of the 2 noise for N smaller 3 ...

Page 153

... ST10F273M Figure 47. ST10F273M PLL jitter ±5 ±4 ±3 ±2 ±1 T JIT 0 0 24.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a ...

Page 154

... SS A Value Min Max 250 2000 500 4000 Value Min Typ Max – 0.4 – – 0.25 – DD – ST10F273M Resonator 27pF 33pF 39pF 840 Ω 1000 Ω 1180 Ω 580 Ω Unit kHz Unit mA 47pF 1200 Ω ...

Page 155

... -40 to +125° Parameter Conditions Start-up (1) Normal run (2) Peak to peak (2) Sine wave middle (2) Stable V DD ST10F273M Crystal 12pF C = 15pF not include the stray capacitance of the package and of the A Electrical characteristics ), the package and the stray 0 Value ...

Page 156

... OSC – – – – IL2 IH2 t 2 Direct drive with PLL usage prescaler CPU XTAL CPU XTAL Min Max Min 10 250 100 3 – – 6 – 2 – – 2 – and V . IH2 IL2 t OSC ST10F273M x F Unit Max 250 – – ...

Page 157

... ST10F273M 24.8.14 Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes how these variables are to be computed. Table 70. Memory cycle variables ...

Page 158

... TCL - 5 -5 – -5 – 1.5 – 14 – – – 2TCL - 9 – 3TCL - 9 – 2TCL - – – 16 ST10F273M Variable CPU clock 1/2 TCL = MHz Unit Max – 3TCL - – 3TCL - – 4TCL - – – 2TCL - 8 – C – F – F – – ...

Page 159

... ST10F273M Table 71. Multiplexed bus timings (continued) Symbol Parameter Address hold after RdCS, WrCS t CC Data hold after WrCS MHz CPU TCL = 12.5ns 1/2 TCL = MHz Min Max Min – 2TCL - – 2TCL - Electrical characteristics Variable CPU clock Unit Max – – ...

Page 160

... Electrical characteristics Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH 160/182 Address Address Address ST10F273M Data in Address Data out ...

Page 161

... ST10F273M Figure 52. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RD Write cycle Address/Data Bus (P0) WR WRL WRH Address t 7 Address Address Electrical characteristics Data Data out ...

Page 162

... Electrical characteristics Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS ALE A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx 162/182 Address Address Address ST10F273M Address Data Data out ...

Page 163

... ST10F273M Figure 54. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx Address t 7 Address Address Electrical characteristics Data Data out 163/182 ...

Page 164

... A C – – – 16 – – – – – – ST10F273M Variable CPU Clock 1/2 TCL = MHz Min Max TCL - 8 – A TCL - – A 2TCL - 12 – A TCL - – A 2TCL - 9 – C 3TCL - 9 – C – 2TCL - – 3TCL - – 3TCL - – 4TCL - – – ...

Page 165

... ST10F273M Table 72. Demultiplexed bus timings (continued) Symbol Parameter Latched CS low to Valid Data in Latched CS hold after RD Address setup to RdCS WrCS 82 (with RW-delay) Address setup to RdCS WrCS 83 (no RW-delay) RdCS to Valid Data (with RW-delay) RdCS to Valid Data (no RW-delay) RdCS, WrCS Low Time t CC ...

Page 166

... Electrical characteristics Figure 55. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 166/182 Address Data out 41u t ( 28h t 18 Data ST10F273M ...

Page 167

... ST10F273M Figure 56. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE CLKOUT ALE t CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH Address Electrical characteristics Data Data out 167/182 ...

Page 168

... Electrical characteristics Figure 57. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 168/182 Address Data out Data ST10F273M ...

Page 169

... ST10F273M Figure 58. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx Address Electrical characteristics Data Data out 169/182 ...

Page 170

... TCL = MHz Max Min Max 25 2TCL 2TCL – TCL – 3.5 – – TCL – 2.5 – 4 – – – – 17 – – 2 – – 2TCL + 10 – – 17 – – 2 – refer to the next following bus cycle ST10F273M Unit refers F ...

Page 171

... ST10F273M Figure 59. CLKOUT and READY CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...

Page 172

... Figure 60. External bus arbitration (releasing the bus) CLKOUT HOLD HLDA BREQ CSx (P6.x) Others 1. The ST10F273M will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t 172/182 f CPU TCL = 12.5ns Parameter ...

Page 173

... This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F273M requesting the bus. 2. The next ST10F273M driven bus cycle may start here. (2) t ...

Page 174

... L (1) Variable baudrate (<SSCBR> = 0001h - FFFFh) Min Max 150 8TCL 262144 TCL – 300 – 300 10 – – – 15 – -2 – 2TCL + 12.5 – 4TCL – 2TCL – 125ns (corresponding to 6.6Mbaud) 300 ST10F273M Unit – – – ns – – – – ...

Page 175

... ST10F273M Figure 62. SSC master timing (1) SCLK MTSR MRST 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). ...

Page 176

... Variable baudrate (<SSCBR> = 0001h - FFFFh) Max Min Max – 6 – 2TCL + 6 (2) 313 t 316 315 Last out bit t t 317 318 Last in bit ST10F273M Unit – ns – ns ...

Page 177

... ST10F273M 25 Package information ® 25.1 ECOPACK In accordance with the RoHS European directive, all STMicroelectronics packages have been converted to lead-free technology, named ECOPACK ® ECOPACK packages have a lead-free second level interconnect. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...

Page 178

... PQFP144 ST10F273M OUTLINE AND MECHANICAL DATA PQFP144 0.10mm .004 Seating Plane C K ...

Page 179

... ST10F273M Figure 65. LQFP144 mechanical data and package dimensions DIM. MIN. TYP 0.05 A2 1.35 B 0.17 C 0.09 D 22.00 D1 20.00 D3 17. 22.00 E1 20.00 E3 17. Note 1: Exact shape of each corner is optional. mm inch MAX. MIN. TYP. MAX. 1.60 0.063 0.15 0.002 0.006 1.40 1.45 0.053 ...

Page 180

... Ordering information 26 Ordering information Table 77. Order codes Order code ST10F273M-4Q3 ST10F273M-4QR3 ST10F273M-4T3 ST10F273M-4TR3 180/182 Package Packing Tray PQFP144 Tape and reel Tray LQFP144 Tape and reel ST10F273M Temperature CPU frequency range range -40 to +125° MHz ...

Page 181

... ST10F273M 27 Revision history Table 78. Document revision history Date Revision 03-May-2007 02-Jul-2007 1 Initial release Changed document status from Preliminary Data to Datasheet Section 4: Memory organization on page - changed size of B0TF from 8 to 4Kbytes - removed ‘Flash Temporary Unprotection’ from X-Miscellaneous features Table 2: Summary of IFlash address range on page ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 182/182 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST10F273M ...