MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet
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MC9S08JM16 MC9S08JM8 Data Sheet HCS08 Microcontrollers MC9S08JM16 Rev. 2 5/2008 freescale.com ...
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MC9S08JM16 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 48 MHz HCS08 CPU (central processor unit) • 24 MHz internal bus frequency • HC08 instruction set with added BGND instruction • Background debugging system • Breakpoint capability to allow ...
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MC9S08JM16 Data Sheet Covers: MC9S08JM16 MC9S08JM8 MC9S08JM16 Rev. 2 5/2008 ...
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... Initial release. Rev. 2 5/2008 Added EMC data in appendix. This product incorporates SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. 6 Description of Changes ® technology licensed from SST. MC9S08JM16 Series Data Sheet, Rev. 2 ...
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... Chapter 15 16-Bit Serial Peripheral Interface (S08SPI16V1 239 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2 267 Chapter 17 Universal Serial Bus Device Controller (S08USBV1 295 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Appendix A Electrical Characteristics........................................................... 349 Appendix B Ordering Information and Mechanical Drawings..................... 373 Freescale Semiconductor List of Chapters Title MC9S08JM16 Series Data Sheet, Rev. 2 Page 7 ...
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... On-Chip Peripheral Modules in Stop Modes ....................................................................35 4.1 MC9S08JM16 Series Memory Map ...............................................................................................37 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................39 4.2 Register Addresses and Bit Assignments ........................................................................................40 4.3 RAM (System RAM) ......................................................................................................................46 4.4 USB RAM .......................................................................................................................................47 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections , ...
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... System Options Register 2 (SOPT2) ................................................................................72 5.7.6 System Device Identification Register (SDIDH, SDIDL) ................................................73 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................74 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................75 6.1 Introduction .....................................................................................................................................77 10 Chapter 5 Chapter 6 Parallel Input/Output MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Extended Addressing Mode (EXT) ................................................................................104 7.3.6 Indexed Addressing Mode ..............................................................................................104 7.4 Special Operations .........................................................................................................................105 7.4.1 Reset Sequence ...............................................................................................................105 7.4.2 Interrupt Sequence ..........................................................................................................105 7.4.3 Wait Mode Operation ......................................................................................................106 7.4.4 Stop Mode Operation ......................................................................................................106 7.4.5 BGND Instruction ...........................................................................................................107 Freescale Semiconductor Chapter 7 MC9S08JM16 Series Data Sheet, Rev ...
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... Analog Power (V 10.2.2 Analog Ground (V 10.2.3 Voltage Reference High (V 10.2.4 Voltage Reference Low (V 10.2.5 Analog Channel Inputs (ADx) ........................................................................................139 12 Chapter 8 Keyboard Interrupt (S08KBIV2) Chapter 9 Chapter 10 ) ..................................................................................................139 DDAD ) .................................................................................................139 SSAD ) ...................................................................................139 REFH ) ....................................................................................139 REFL MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... IIC Control Register (IICC1) ..........................................................................................166 11.3.4 IIC Status Register (IICS) ...............................................................................................166 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................167 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................168 11.4 Functional Description ..................................................................................................................169 11.4.1 IIC Protocol .....................................................................................................................169 11.4.2 10-bit Address .................................................................................................................172 Freescale Semiconductor Chapter 11 MC9S08JM16 Series Data Sheet, Rev ...
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... External Signal Description ..........................................................................................................212 13.3 Register Definition ........................................................................................................................212 13.3.1 RTC Status and Control Register (RTCSC) ....................................................................213 13.3.2 RTC Counter Register (RTCCNT) ..................................................................................214 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................214 13.4 Functional Description ..................................................................................................................214 14 Chapter 12 Chapter 13 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... SPI Baud Rate Register (SPIxBR) ..................................................................................248 15.3.4 SPI Status Register (SPIxS) ............................................................................................249 15.3.5 SPI Data Registers (SPIxDH:SPIxDL) ...........................................................................250 15.3.6 SPI Match Registers (SPIxMH:SPIxML) .......................................................................251 15.4 Functional Description ..................................................................................................................252 15.4.1 General ............................................................................................................................252 Freescale Semiconductor Chapter 14 Chapter 15 MC9S08JM16 Series Data Sheet, Rev ...
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... Universal Serial Bus Device Controller (S08USBV1) 17.1 Introduction ...................................................................................................................................295 17.1.1 Clocking Requirements ...................................................................................................295 17.1.2 Current Consumption in USB Suspend ..........................................................................295 17.1.3 3.3 V Regulator ...............................................................................................................295 17.1.4 Features ...........................................................................................................................298 17.1.5 Modes of Operation ........................................................................................................298 17.1.6 Block Diagram ................................................................................................................299 16 Chapter 16 Chapter 17 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Comparators A and B .....................................................................................................337 18.3.2 Bus Capture Information and FIFO Operation ...............................................................337 18.3.3 Change-of-Flow Information ..........................................................................................338 18.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................338 18.3.5 Trigger Modes .................................................................................................................339 18.3.6 Hardware Breakpoints ....................................................................................................341 Freescale Semiconductor Chapter 18 Development Support MC9S08JM16 Series Data Sheet, Rev ...
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... A.14 USB Electricals ..............................................................................................................................369 18.5 EMC Performance .........................................................................................................................370 18.5.1 Radiated Emissions .........................................................................................................370 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................373 B.2 Orderable Part Numbering System ................................................................................................373 B.3 Mechanical Drawings.....................................................................................................................373 18 Appendix A Electrical Characteristics Appendix B MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... SCI1 SCI2 yes SPI1 SPI2 yes TPM1 4-ch TPM2 USB I/O pins 37 Package types 48 QFN 1.2 MCU Block Diagram The block diagram in Figure 1-1 Freescale Semiconductor Device MC9S08JM16 44-pin 32-pin 16,384 1024 256 yes 8-ch 4-ch yes yes 7 5 yes no yes ...
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... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 2 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
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... The FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. 2. ADC has min. and max. frequency requirements. See Characteristics,” for details. 3. Flash has frequency requirements for program and erase operation. See Figure 1-2. System Clock Distribution Diagram Freescale Semiconductor Table 1-2. Versions of On-Chip Modules Module (ACMP) (ADC) ...
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... Watchdog,” for details on using the LPO clock with these modules. (S08TPMV2),” for more details. MC9S08JM16 Series Data Sheet, Rev. 2 (S08MCGV1),” explains the (S08RTCV1),” for more Clock,” explains the MCGERCLK in Chapter 10, Section 12.4.7, “Fixed Frequency Section 5.4, “Computer Chapter 16, Freescale Semiconductor ...
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... QFN pin assignments for the MC9S08JM16. See availability by package pin count. 48 PTC4 1 IRQ/TPMCLK 2 RESET 3 PTF0/TPM1CH2 4 PTF1/TPM1CH3 5 PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 PTF6 8 PTE0/TxD1 9 PTE1/RxD1 10 PTE2/TPM1CH0 11 PTE3/TPM1CH1 12 13 Figure 2-1. MC9S08JM16 Series in 48-Pin QFN Package Freescale Semiconductor 48-Pin QFN MC9S08JM16 Series Data Sheet, Rev. 2 Table 2-1 for pin 37 38 PTD2/KBIP2/ACMPO ...
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... LQFP pin assignments for the MC9S08JM16 devices. See availability by package pin count 44-Pin LQFP MC9S08JM16 Series Data Sheet, Rev. 2 Table 2 PTD2/KBIP2/ACMPO SSAD REFL DDAD REFH PTD1/ADP9/ACMP– PTD0/ADP8/ACMP+ 28 PTB5/KBIP5/ADP5 PTB4/KBIP4/ADP4 27 26 PTB3/SS2/ADP3 PTB2/SPSCK2/ADP2 25 PTB1/MOSI2/ADP1 24 PTB0/MISO2/ADP0 Table 2-1 Freescale Semiconductor for pin for pin ...
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... IRQ/TPMCLK RESET PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 Figure 2-3. MC9S08JM16 Series in 32-Pin LQFP Package 2.3 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08JM16 series application systems. Freescale Semiconductor 32-Pin LQFP MC9S08JM16 Series Data Sheet, Rev. 2 ...
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... PTC5/RxD2 I/O AND PTD0/ADP8/ACMP+ PERIPHERAL PTD1/ADP9/ACMP– PTD2/KBIP2/ACMPO PORT INTERFACE TO D APPLICATION PTD7 SYSTEM PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 PORT PTE4/MISO1 E PTE5/MOSI1 PTE6/SPSCK1 PTE7/SS1 PTF0/TPM1CH2 PTF1/TPM1CH3 PORT F PTF4/TPM2CH0 PTF5/TPM2CH1 PTF6 PTG0/KBIP0 PTG1/KBIP1 PORT PTG2/KBIP6 G PTG3/KBIP7 PTG4/XTAL PTG5/EXTAL are enabled. PUDP Freescale Semiconductor ...
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... C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 (which are usually the same size first-order approximation, use estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). Freescale Semiconductor , ...
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... The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin can be used for TPMCLK. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See an example REFH REFL MC9S08JM16 Series Data Sheet, Rev. 2 Figure 2-4 Figure 2-4 for Freescale Semiconductor ...
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... The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. Freescale Semiconductor NOTE Table 2-1 illustrates the priority if multiple modules MC9S08JM16 Series Data Sheet, Rev ...
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... PTD1 ADP9 ACMP– V DDAD 22 V REFH V REFL 23 V SSAD 24 PTD2 KBIP2 ACMPO — PTD7 25 PTG2 KBIP6 26 PTG3 KBIP7 27 BKGD MS 28 PTG4 XTAL 29 PTG5 EXTAL 30 V SSOSC 31 PTC0 SCL 32 PTC1 SDA — PTC2 — PTC3 TxD2 — PTC5 RxD2 Freescale Semiconductor ...
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... Section 5.7.3, “System Background Debug Force Reset Register • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 (SBDFR)”) 31 ...
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... The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in stop or wait mode. • The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 32 MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 18, “Development Freescale Semiconductor ...
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... CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will enter stop3 instead. For the ADC to operate the LVD must be left enabled when entering stop3. Freescale Semiconductor Table 3-1. Stop Mode Selection LVDSE ...
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... PPDF remains set and the I/O pin states remain latched until written to PPDACK in SPMSC2. 34 Support.” If ENBDM is set when the CPU executes a NOTE MC9S08JM16 Series Data Sheet, Rev. 2 Table 3-1. Most is below the LVD DD Freescale Semiconductor ...
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... If ACGBS in ACMPSC is set, LVD must be enabled, else in standby. 3 IRCLKEN and IREFSTEN set in MCGC1, else in standby. 4 RTCPS[3:0] in RTCSC does not equal to 0 before entering stop, else off. Freescale Semiconductor Mode,” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Mode Stop2 ...
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... Chapter 3 Modes of Operation 5 ERCLKEN and EREFSTEN set in MCGC2, else in standby. For high frequency range (RANGE in MCGC2 set), it also requires the LVD to be enabled in stop3. 6 USBEN in CTL is set and USBPHYEN in USBCTL0 is set, else off. 36 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x00AF) • High-page registers (0x1800 through 0x185F) • Nonvolatile registers (0xFFB0 through 0xFFBF) Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev ...
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... MC9S08JM16 Series Data Sheet, Rev. 2 MC9S08JM8 Direct Page Registers RAM 1,024 Bytes Unimplemented Unimplemented High Page Registers USB RAM — 256 BYTES Unimplemented Flash 8,192 bytes Freescale Semiconductor ...
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... Freescale Semiconductor Table 4-1. Reset and Interrupt Vectors Vector Unused Vector Space RTC IIC ACMP ADC Conversion KBI SCI2 Transmit SCI2 Receive SCI2 Error SCI1 Transmit SCI1 Receive ...
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... Vector MCG Loss of Lock Low Voltage Detect IRQ SWI Reset can use more efficient direct addressing mode, which requires only MC9S08JM16 Series Data Sheet, Rev. 2 Vector Name Vlol Vlvd Virq Vswi Vreset Table 4 summary of all Table 4-2, Table Freescale Semiconductor 4-3, ...
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... TPM1MODH Bit 15 0x0024 TPM1MODL Bit 7 0x0025 TPM1C0SC CH0F 0x0026 TPM1C0VH Bit 15 0x0027 TPM1C0VL Bit 7 0x0028 TPM1C1SC CH1F 0x0029 TPM1C1VH Bit 15 Freescale Semiconductor — PTAD5 — — PTADD5 — — PTBD5 PTBD4 — PTBDD5 PTBDD4 — PTCD5 PTCD4 — PTCDD5 PTCDD4 — ...
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... CPOL CPHA SSOE BIDIROE 0 SPISWAI 0 SPR2 SPR1 AD3 AD2 AD1 Freescale Semiconductor Bit 0 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 IREFSTEN FTRIM 0 — LSBFE SPC0 ...
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... USBCTL0 USBRESET 0x0081 – Reserved — 0x0087 0x0088 PERID 0 0x0089 IDCOMP 1 0x008A REV REV7 0x008B – Reserved — 0x008F STALLF 0x0090 INTSTAT 0x0091 INTENB STALL Freescale Semiconductor IICIE MST TX IAAS BUSY ARBL DATA ADEXT 0 0 — — — TOIE CPWMS CLKSB ...
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... LVDSE LVDE 0 PPDF PPDACK — — — — Freescale Semiconductor 1 Bit 0 PIDERRF PIDERR 0 0 USBEN ADDR0 FRM0 FRM8 — EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK — Bit 0 — BDFR — ACIC — ID8 ID0 — 1 BGBE PPDC — ...
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... PTFSE — 0x1856 PTFDS — 0x1857 Reserved — 0x1858 PTGPE — 0x1859 PTGSE — 0x185A PTGDS — 0x185B – Reserved — 0x185F Freescale Semiconductor ARM TAG BRKEN BEGIN ARMF 0 — — — PRDIV8 DIV5 DIV4 FNORED 0 0 — — ...
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... FPS6 FPS5 FPS4 — — — FNORED 0 0 MC9S08JM16 Series Data Sheet, Rev Bit FTRIM — — — — — — FPS3 FPS2 FPS1 FPDIS — — — SEC01 SEC00 Freescale Semiconductor — — — ...
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... Because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1. 4.5.1 ...
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... FCLK FCLK FCLK Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 NOTE MC9S08JM16 Series Data Sheet, Rev The times are shown as a number = 5 μs. Program and erase times Time if FCLK = 200 kHz 45 μs 20 μ 100 ms Freescale Semiconductor ...
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... The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the flash array does not need to be disabled between program operations. Ordinarily, when a program or erase command Freescale Semiconductor is a flowchart for executing all of the commands except for burst 1 ...
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... This is because the high voltage to the array must be disabled and then enabled again new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage will be removed from the array. 50 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Writing to a flash address before the internal flash clock frequency has been set by writing to the FCDIV register • Writing to a flash address while FCBEF is not set (a new command cannot be started until the command buffer is empty) Freescale Semiconductor 1 WRITE TO FCDIV START 0 FACCERR? ...
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... Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 A13 52 NVPROT).”) 1 A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08JM16 Series Data Sheet, Rev. 2 Section 4.7.4, “Flash Freescale Semiconductor ...
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... BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 4 Memory ...
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... This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 54 MC9S08JM16 Series Data Sheet, Rev. 2 Table 4-3 and Table 4-4 for the Freescale Semiconductor ...
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... The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation if PRDIV8 = 0 – PRDIV8 = 1 – f Table 4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies. Freescale Semiconductor DIV5 DIV4 DIV3 0 ...
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... Min, 6.7 μs Max) FCLK 5 μs 200 kHz 5.2 μs 192.3 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 6.7 μs 150 kHz SEC01 “Security.” Table Freescale Semiconductor 0 SEC00 4-9. When ...
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... Background debug commands can write to FPROT FPS7 FPS6 Reset This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. Flash Protection Register (FPROT) Freescale Semiconductor Table 4-9. Security States Description 0:0 0:1 1:0 Unsecured 1 KEYACC ...
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... FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. 58 Description FPVIOL FACCERR Figure 4-9. Flash Status Register (FSTAT) Description MC9S08JM16 Series Data Sheet, Rev FBLANK Freescale Semiconductor ...
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... Command Blank check Byte program Byte program — burst mode Page erase (512 bytes/page) Mass erase (all flash) All other command codes are illegal and generate an access error. Freescale Semiconductor Description Section 4.5.5, “Access Execution,” for a detailed discussion of flash programming ...
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... Chapter 4 Memory It is not necessary to perform a blank check command after a mass erase operation. Blank check is required only as part of the security unlocking mechanism. 60 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug forced reset • External reset pin (RESET) • Clock generator loss of lock and loss of clock reset (LOC) Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Table 5-1) 61 ...
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... Section 5.7.4, “System Options Register 1 Section 5.7.5, “System Options Register 2 Table 5-6 summaries the control functions of the COPCLKS and MC9S08JM16 Series Data Sheet, Rev. 2 (SOPT1),” (SOPT2),” for additional Freescale Semiconductor ...
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... RTI that is used to return from the ISR. If two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-1). Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE MC9S08JM16 Series Data Sheet, Rev ...
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... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08JM16 Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... Vkeyboard Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE DD – 0.7 V. The internal gates connected to this pin are pulled . DD Module Source Unused vector space (available for user program) System Vrtc RTIF control Viic ...
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... TPM2 channel 1 CH0IE TPM2 channel 0 TOIE TPM1 overflow reserved reserved reserved reserved CH3IE TPM1 channel 3 CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — STALL RESUME SLEEP TOKDNE USB Status SOFTOK ERROR USBRST SPIE SPIE SPI2 SPTIE SPMIE Freescale Semiconductor ...
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... LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following an LVD reset or POR. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Module ...
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... Unimplemented or Reserved Figure 5-2. Interrupt Request Status and Control Register (IRQSC and one low (V LVWH Chapter 4, “Memory,” of this data sheet for the absolute IRQF IRQEDG IRQPE MC9S08JM16 Series Data Sheet, Rev The trip voltage is LVWL IRQIE IRQMOD IRQACK Freescale Semiconductor ...
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... BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description Sensitivity,” ...
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... WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00 COP ILOP Writing any value to SRS address clears COP watchdog timer (1) (1) Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Description MC9S08JM16 Series Data Sheet, Rev LOC LVD ( Freescale Semiconductor 0 — ...
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... Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is STOPE disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... See t in the appendix LPO LPO Description MC9S08JM16 Series Data Sheet, Rev. 2 COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles Section A.12.1, “Control Timing,” for the 2 1 SPI1FE SPI2FE ACIC 1 1 Freescale Semiconductor 0 0 ...
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... Table 5-9. SDIDL Register Field Descriptions Field 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08JM16 series is hard coded to the value 0x01E. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description ID11 — ...
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... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled LVWIE LVDRE LVDSE transitions below the trip point or after reset and V Supply Description MC9S08JM16 Series Data Sheet, Rev LVDE BGBE already below V . Supply LVW Freescale Semiconductor ...
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... Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Table 5-12. LVD and LVW Trip Point Typical Values LVDV:LVWV 0:0 0:1 1:0 1:1 1 See Electrical Characteristics appendix for minimum and maximum values. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration PPDF LVDV LVWV 0 0 ...
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... Chapter 5 Resets, Interrupts, and System Configuration 76 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Freescale Semiconductor Chapter 2, “Pins and Table 2-1 to determine which functions are available for a NOTE MC9S08JM16 Series Data Sheet, Rev ...
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... Write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened the port data register. 78 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08JM16 Series Data Sheet, Rev. 2 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
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... PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user’s application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 6 Parallel Input/Output 79 ...
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... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTAD5 0 0 Figure 6-2. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Description 5 4 PTADD5 0 0 Description MC9S08JM16 Series Data Sheet, Rev Freescale Semiconductor 0 PTAD0 0 0 PTADD0 0 ...
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... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit Reset 0 0 Figure 6-6. Output Drive Strength Selection for Port A (PTASE) Freescale Semiconductor PTAPE5 Description ...
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... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. 82 Description 5 4 PTBD5 PTBD4 PTBD3 0 0 Figure 6-7. Port B Data Register (PTBD) Table 6-6. PTBD Register Field Descriptions Description 5 4 PTBDD5 PTBDD4 PTBDD3 0 0 Description MC9S08JM16 Series Data Sheet, Rev PTBD2 PTBD1 PTBDD2 PTBDD1 Freescale Semiconductor 0 PTBD0 0 0 PTBDD0 0 ...
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... PTBSE[5:0] rate control is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Freescale Semiconductor PTBPE5 PTBPE4 ...
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... Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled PTBDS5 PTBDS4 PTBDS3 Description PTCD5 PTCD4 PTCD3 Figure 6-12. Port C Data Register (PTCD) Description MC9S08JM16 Series Data Sheet, Rev PTBDS2 PTBDS1 PTBDS0 PTCD2 PTCD1 PTCD0 Freescale Semiconductor ...
Page 85
... PTC pin. For port C pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port C bit n. 1 Internal pullup device enabled for port C bit n. Freescale Semiconductor ...
Page 86
... PTC pin. 0 Low output drive enabled for port C bit n. 1 High output drive enabled for port C bit PTCSE5 PTCSE4 PTCSE3 Description PTCDS5 PTCDS4 PTCDS3 Description MC9S08JM16 Series Data Sheet, Rev PTCSE2 PTCSE1 PTCSE0 PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...
Page 87
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7, 2:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor ...
Page 88
... PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit Description Description MC9S08JM16 Series Data Sheet, Rev PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 89
... Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...
Page 90
... Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn PTEDD5 PTEDD4 PTEDD3 Description MC9S08JM16 Series Data Sheet, Rev PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 91
... PTESE[7:0] rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. Freescale Semiconductor PTEPE5 PTEPE4 ...
Page 92
... Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled PTEDS5 PTEDS4 PTEDS3 Description PTFD5 PTFD4 Figure 6-27. Port F Data Register (PTFD) Description MC9S08JM16 Series Data Sheet, Rev PTEDS2 PTEDS1 PTEDS0 PTFD1 PTFD0 Freescale Semiconductor ...
Page 93
... PTF pin. For port F pins that are configured as outputs, these bits have no effect and [6:4, 1:0] the internal pullup devices are disabled. 0 Internal pullup device disabled for port F bit n. 1 Internal pullup device enabled for port F bit n. Freescale Semiconductor PTFDD5 ...
Page 94
... PTF pin. [6:4, 1:0] 0 Low output drive enabled for port F bit n. 1 High output drive enabled for port F bit PTFSE5 PTFSE4 Description PTFDS5 PTFDS4 Description MC9S08JM16 Series Data Sheet, Rev PTFSE1 PTFSE0 PTFDS1 PTFDS0 Freescale Semiconductor ...
Page 95
... Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for PTGDD[5:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. Freescale Semiconductor PTGD5 ...
Page 96
... PTG pin. For port G pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit PTGPE5 PTGPE4 PTGPE3 Description PTGSE5 PTGSE4 PTGSE3 Description MC9S08JM16 Series Data Sheet, Rev PTGPE2 PTGPE1 PTGPE0 PTGSE2 PTGSE1 PTGSE0 Freescale Semiconductor ...
Page 97
... Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDSn output drive for the associated PTG pin. 0 Low output drive enabled for port G bit n. 1 High output drive enabled for port G bit n. Freescale Semiconductor PTGDS5 ...
Page 98
... Chapter 6 Parallel Input/Output 98 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 99
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
Page 100
... X. 100 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 101
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 102
... No carry out of bit 7 1 Carry out of bit 7 102 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 103
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 104
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 104 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 105
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08JM16 Series Data Sheet, Rev. 2 ...
Page 106
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 106 chapter for more details. MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 107
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 108
... rpp prpp prpp 0 – – rpp 3 F4 rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 77 rfwp prfwpp 3 – – – – – – ppp Freescale Semiconductor Affect on CCR – – – – – – – ...
Page 109
... BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( BPL rel Branch if Plus ( Freescale Semiconductor Operation Object Code DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) ...
Page 110
... AD rr ssppp rpppp pppp pppp – – – – – – rpppp rfppp prpppp 1 – – – – – – – 0 – – – rfwpp – – – rfwpp 4 7F rfwp prfwpp Freescale Semiconductor Affect on CCR ...
Page 111
... A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 M ← (M)= $FF – (M) ...
Page 112
... AE prrfp pprrpp prrpp prrpp rpp prpp prpp 0 – – rpp 3 FE rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 74 rfwp prfwpp Freescale Semiconductor Affect on CCR – – – – – – – – – – 0 ...
Page 113
... ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8,X b7 ROR ,X ROR oprx8,SP Freescale Semiconductor Operation Object Code DIR/DIR DIR/IX+ source IMM/DIR IX+/DIR INH M ← – (M) = $00 – (M) DIR INH X ← – (X) = $00 – (X) INH M ← ...
Page 114
... B7 dd wpp pwpp pwpp 3 0 – wpp ppwpp pwpp wwpp 5 0 – pwwpp pwwpp 2 – – 0 – – – 8E fp... wpp pwpp pwpp 3 0 – wpp ppwpp pwpp Freescale Semiconductor Affect on CCR – – – – – – – – ...
Page 115
... TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 INH INH ...
Page 116
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: Set or cleared – Not affected U Undefined MC9S08JM16 Series Data Sheet, Rev. 2 Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – 8F fp... Freescale Semiconductor ...
Page 117
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 118
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 119
... Connections,” for more information about the logic and hardware aspects of these pins. MC9S08JM16 series devices operate at a higher voltage range (2 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. Freescale Semiconductor NOTE MC9S08JM16 Series Data Sheet, Rev. 2 Chapter 2, ...
Page 120
... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 2 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
Page 121
... KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 8.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown Freescale Semiconductor Figure MC9S08JM16 Series Data Sheet, Rev. 2 Keyboard Interrupts (S08KBIV2) Modes of Operation 8-2 ...
Page 122
... Figure 8-2. KBI Block Diagram Table 8-1. Table 8-1. Signal Properties Function Keyboard interrupt pins Memory chapter for the absolute address assignments for MC9S08JM16 Series Data Sheet, Rev. 2 BUSCLK KBF SYNCHRONIZER STOP BYPASS KBI STOP INTERRUPT REQUES T KBIE I/O I Freescale Semiconductor ...
Page 123
... Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. KBIPEn 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 8.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. Freescale Semiconductor KBF 0 0 Figure 8-3 ...
Page 124
... A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing KBACK in 124 KBEDG5 KBEDG4 KBEDG3 Figure 8-5. KBI Edge Select Register Description MC9S08JM16 Series Data Sheet, Rev KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...
Page 125
... If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Keyboard Interrupts (S08KBIV2) 125 ...
Page 126
... Keyboard Interrupts (S08KBIV2) 126 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 127
... The ACMP module can be configured to connect the output of the analog comparator to TPM input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM module. Freescale Semiconductor NOTE Section 5.7.7, “System Power Management Status and Control 1 MC9S08JM16 Series Data Sheet, Rev. 2 Appendix A.6, “ ...
Page 128
... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 2 TPM1CHx RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
Page 129
... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 9.1.5 Block Diagram The block diagram for the Analog Comparator module is shown Freescale Semiconductor Figure MC9S08JM16 Series Data Sheet, Rev. 2 Analog Comparator (S08ACMPV2) 9-2. ...
Page 130
... Table 9-1. Table 9-1. Signal Properties Function Inverting analog input to the ACMP. (Minus input) Non-inverting analog input to the ACMP. (Positive input) Digital output of the ACMP. MC9S08JM16 Series Data Sheet, Rev. 2 ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Figure 9-2, I Freescale Semiconductor ...
Page 131
... ACF is set. 0 Interrupt disabled 1 Interrupt enabled 3 Analog Comparator Output — Reading ACO will return the current value of the analog comparator output. ACO ACO is reset and will read when the ACMP is disabled (ACME = 0). Freescale Semiconductor ACO ACF ACIE ...
Page 132
... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. 132 Description MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 133
... AD10 V REFL 01011 AD11 V REFL 01100 AD12 V REFL 01101 AD13 V REFL 01110 AD14 V REFL Freescale Semiconductor NOTE Table 10-1. ADC Channel Assignment Pin Control ADCH ADPC0 10000 ADPC1 10001 ADPC2 10010 ADPC3 10011 ADPC4 10100 ADPC5 10101 ADPC6 10110 ADPC7 ...
Page 134
... Pin Control ADCH ADPC15 11111 Sensor.” NOTE Electricals.” ) after being divided down from the ALTCLK input as ADCK ) ÷ m) – V TEMP TEMP25 MC9S08JM16 Series Data Sheet, Rev. 2 Channel Input Pin Control module None disabled Appendix A.8, Eqn. 10-1 Freescale Semiconductor N/A ...
Page 135
... Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) and m values from the TEMP25 the cold slope value is applied in ...
Page 136
... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 2 TPM1CHx RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
Page 137
... Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.4 ADC Module Block Diagram Figure 10-2 provides a block diagram of the ADC module Freescale Semiconductor . MC9S08JM16 Series Data Sheet, Rev. 2 Analog-to-Digital Converter (S08ADC12V1) 137 ...
Page 138
... Function AD27 – AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08JM16 Series Data Sheet, Rev. 2 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...
Page 139
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 140
... ADCO Table 10-3. ADCSC1 Field Descriptions Description Table 10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 V REFH 11110 V REFL 11111 Module disabled MC9S08JM16 Series Data Sheet, Rev ADCH Freescale Semiconductor ...
Page 141
... ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL. Freescale Semiconductor 5 4 ...
Page 142
... These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare. 142 ADR11 ADR5 ADR4 ADR3 ADCV11 MC9S08JM16 Series Data Sheet, Rev ADR10 ADR9 ADR8 ADR2 ADR1 ADR0 ADCV10 ADCV9 ADCV8 Freescale Semiconductor ...
Page 143
... Long sample time 3:2 Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See MODE 1:0 Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See ADICLK Table 10-9. Freescale Semiconductor ADCV5 ADCV4 ADCV3 0 0 ...
Page 144
... Selected Clock Source Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) Asynchronous clock (ADACK ADPC5 ADPC4 ADPC3 Description MC9S08JM16 Series Data Sheet, Rev. 2 Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ ADPC2 ADPC1 ADPC0 Freescale Semiconductor ...
Page 145
... ADC Pin Control 14. ADPC14 controls the pin associated with channel AD14. ADPC14 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADC Pin Control 13. ADPC13 controls the pin associated with channel AD13. ADPC13 0 AD13 pin I/O control enabled 1 AD13 pin I/O control disabled Freescale Semiconductor Description ADPC13 ADPC12 ADPC11 0 ...
Page 146
... AD21 pin I/O control disabled 4 ADC Pin Control 20. ADPC20 controls the pin associated with channel AD20. ADPC20 0 AD20 pin I/O control enabled 1 AD20 pin I/O control disabled 146 Description ADPC21 ADPC20 ADPC19 Description MC9S08JM16 Series Data Sheet, Rev ADPC18 ADPC17 ADPC16 Freescale Semiconductor ...
Page 147
... The bus clock divided by two. For higher bus clock rates, this allows a maximum divide the bus clock. • ALTCLK, as defined for this MCU (See module section introduction). Freescale Semiconductor Description MC9S08JM16 Series Data Sheet, Rev. 2 Analog-to-Digital Converter (S08ADC12V1) 147 ...
Page 148
... Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected. • Following the transfer of the result to the data registers when continuous conversion is enabled. 148 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 149
... The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, the ADACK clock generator is also enabled. Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value for f (see the electrical specifications). ADCK Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Analog-to-Digital Converter (S08ADC12V1) 149 ...
Page 150
... ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles = 3.5 μs 8 MHz Freescale Semiconductor ). f ADCK ...
Page 151
... Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL Freescale Semiconductor NOTE minimum and f ADCK NOTE MC9S08JM16 Series Data Sheet, Rev ...
Page 152
... Table 10-8, and Table 10-9 for information used in this example. Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 152 NOTE Section 10.4.4.2, “Completing NOTE MC9S08JM16 Series Data Sheet, Rev. 2 Table 10-7, Freescale Semiconductor ...
Page 153
... ADCCVH/L = 0xxx Holds compare value when compare function enabled Freescale Semiconductor Configures for low power (lowers maximum clock speed) Sets the ADCK to the input clock ÷ 1 Configures for long sample time ...
Page 154
... MCU digital V SSAD 154 Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 No Check COCO=1? Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue DDAD MC9S08JM16 Series Data Sheet, Rev. 2 and V ) available as separate pins SSAD on some devices. On other SS Freescale Semiconductor ...
Page 155
... For proper conversion, the input voltage must fall between V exceeds V , the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF REFH (full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less Freescale Semiconductor and V must be connected to the same voltage potential DDAD SSAD ...
Page 156
... REFH REFL to V DDAD SSAD at a quiet point in the ground plane. SS MC9S08JM16 Series Data Sheet, Rev. 2 and V are REFH REFL when the sampling REFL ) is kept high for less than DDAD LEAK . . Freescale Semiconductor DD ...
Page 157
... If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its ideal ( used. LSB • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. Freescale Semiconductor ) on the selected input channel lsb = (V – ...
Page 158
... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. 158 reduces this error. MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 159
... The two pins associated with this module, SCL and SDA, are shared with PTC0 and PTC1, respectively. MC9S08JM16 devices operate at a higher voltage range (2 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. Freescale Semiconductor NOTE MC9S08JM16 Series Data Sheet, Rev. 2 159 ...
Page 160
... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 2 TPM1CHx RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
Page 161
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. 11.1.3 Block Diagram Figure 11 block diagram of the IIC. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Inter-Integrated Circuit (S08IICV2) 161 ...
Page 162
... FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram memory chapter of this document for the absolute address MC9S08JM16 Series Data Sheet, Rev. 2 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 163
... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) Freescale Semiconductor AD5 AD4 AD3 Figure 11-3. IIC Address Register (IICA) Table 11-1. IICA Field Descriptions ...
Page 164
... MC9S08JM16 Series Data Sheet, Rev. 2 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...
Page 165
... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 11-4. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 121 3F MC9S08JM16 Series Data Sheet, Rev. 2 ...
Page 166
... IIC Status Register (IICS TCF IAAS W Reset Unimplemented or Reserved 166 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Description BUSY 0 ARBL Figure 11-6. IIC Status Register (IICS) MC9S08JM16 Series Data Sheet, Rev RSTA SRW RXAK IICIF Freescale Semiconductor ...
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... If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received 11.3.5 IIC Data I/O Register (IICD Reset 0 0 Freescale Semiconductor Table 11-6. IICS Field Descriptions Description DATA Figure 11-7. IIC Data I/O Register (IICD) MC9S08JM16 Series Data Sheet, Rev. 2 Inter-Integrated Circuit (S08IICV2) ...
Page 168
... AD[10:8] scheme. This field is only valid when the ADEXT bit is set. 168 Table 11-7. IICD Field Descriptions Description NOTE Figure 11-8. IIC Control Register (IICC2) Table 11-8. IICC2 Field Descriptions Description MC9S08JM16 Series Data Sheet, Rev AD10 AD9 AD8 Freescale Semiconductor ...
Page 169
... As shown in defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. Freescale Semiconductor Figure lsb msb ...
Page 170
... The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 170 11-9. There is one clock pulse on SCL for each data bit, the msb being MC9S08JM16 Series Data Sheet, Rev. 2 Figure 11-9). Freescale Semiconductor ...
Page 171
... The first device to complete its high period pulls the SCL line low again. SCL1 SCL2 SCL Internal Counter Reset Freescale Semiconductor Delay Figure 11-10. IIC Clock Synchronization MC9S08JM16 Series Data Sheet, Rev. 2 Inter-Integrated Circuit (S08IICV2) Figure 11-10) ...
Page 172
... The slave-transmitter remains addressed until it receives a stop condition ( repeated start condition (Sr) followed by a different slave address. 172 Table 11-9). When a 10-bit address follows a start condition, R/W Slave Address 2nd byte AD[8:1] Table MC9S08JM16 Series Data Sheet, Rev. 2 Data A ... Data A/A P 11-10 and including Freescale Semiconductor ...
Page 173
... Complete 1-byte transfer Match of received calling address Arbitration Lost 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. Freescale Semiconductor Slave Address Slave Address 2nd byte 1st 7 bits A2 Sr ...
Page 174
... SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. 174 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 175
... IICEN IICC1 Module configuration TCF IICS Module status flags IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT Address configuration Freescale Semiconductor Module Initialization (Slave) Module Initialization (Master) Register Model AD[7:1] ICR IICIE MST TX TXAK IAAS ...
Page 176
... Clear ARBL Y N IAAS=1 IAAS Data Transfer Address Transfer See Note 2 See Note 1 Y SRW=1 TX/ (Write) N ACK from Y Receiver ? N Read Data Tx Next from IICD Byte and Store Switch to Set RX Rx Mode Mode Dummy Read Dummy Read from IICD from IICD Freescale Semiconductor RX ...
Page 177
... For USB operation on the MC9S08JM60 series, the MCG must be configured for PLL engaged external (PEE) mode using a crystal in order to achieve an MCGOUT frequency of 48 MHz. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 177 ...
Page 178
... ACMP+ PTD0/ADP8/ACMP+ ACMPO SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 2 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 KBIPx 3 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...
Page 179
... Can be selected as the clock source for the MCU • Reference divider is provided • Clock source selected can be divided down • BDC clock (MCGLCLK) is provided as a constant divide the DCO output whether in an FLL or PLL mode. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 179 ...
Page 180
... DCOOUT 9 DCO TRIM PLLS RDIV_CLK Filter FLL LP VCOOUT Charge Phase VCO Pump Detector Internal VDIV Filter PLL /(4,8,12,...,40) Multi-purpose Clock Generator (MCG) MC9S08JM16 Series Data Sheet, Rev. 2 MCGERCLK MCGIRCLK CLKS BDIV MCGOUT n=0-3 Lock Detector LOLS LOCK MCGFFCLK / 2 MCGLCLK Freescale Semiconductor ...
Page 181
... Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details see Section 12.4.1, “Operational 12.2 External Signal Description There are no MCG signals that connect off chip. Freescale Semiconductor Modes.” MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 181 ...
Page 182
... MCG enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before entering stop 0 Internal reference clock is disabled in stop 182 RDIV Description MC9S08JM16 Series Data Sheet, Rev IREFS IRCLKEN IREFSTEN Freescale Semiconductor ...
Page 183
... External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when EREFSTEN the MCG enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or BLPE mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor RANGE HGO ...
Page 184
... An additional fine trim bit is available in MCGSC as the FTRIM bit TRIM[7:0] value stored in nonvolatile memory used, it’s the user’s responsibility to copy that value from the nonvolatile memory location to this register. 184 5 4 TRIM Figure 12-5. MCG Trim Register (MCGTRM) Description MC9S08JM16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 185
... CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of FLL is selected. 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of PLL is selected. Freescale Semiconductor 5 4 PLLST IREFST Description ...
Page 186
... PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all PLLS modes. If the PLLS is set, the FLL is disabled in all modes. 1 PLL is selected 0 FLL is selected 186 Description CME 0 0 Figure 12-7. MCG PLL Register (MCGPLL) Description MC9S08JM16 Series Data Sheet, Rev VDIV Freescale Semiconductor 0 1 ...
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... Encoding 8 — Multiply by 32. 1001 Encoding 9 — Multiply by 36. 1010 Encoding 10 — Multiply by 40. 1011 Encoding 11 — Reserved (default to M=40). 11xx Encoding 12-15 — Reserved (default to M=40). Freescale Semiconductor Description MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 187 ...
Page 188
... CLKS=10 IREFS=0 PLLS=0 CLKS=10 BDM Enabled BDM Disabled or LP=0 and LP=1 Bypassed Low Power External (BLPE) IREFS=0 CLKS=10 PLLS=1 BDM Enabled or LP=0 IREFS=0 CLKS=00 PLLS=1 Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Freescale Semiconductor ...
Page 189
... FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock. The FLL bypassed external mode is entered when all the following conditions occur: Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) ...
Page 190
... VDIV bits, times the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low power state. 190 NOTE 12.5.2.4, “Example # 4: Moving MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 191
... The bypassed low power external (BLPE) mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written • LP bit is written to 1 • BDM mode is not active Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 191 ...
Page 192
... For details see Figure 12-8. 12.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 192 MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 193
... MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and RDIV values: Freescale Semiconductor chapter). MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) Device Overview chapter) ...
Page 194
... For 194 microseconds before the FLL can acquire lock. As soon as the internal milliseconds. fll_lock NOTE Figure 12-8). Reaching any of the other modes requires MC9S08JM16 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 195
... MHz. The RDIV and IREFS bits must always be set properly before changing the PLLS bit so that the FLL or PLL clock has an appropriate reference clock frequency to switch to. Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 195 ...
Page 196
... R must be in the range of ext 31.25 kHz to 39.0625 kHz must be in the range of ext 31.25 kHz to 39.0625 kHz Typical kHz int must be in the range of 1 ext MHz to 2 MHz must be in the range of 1 ext MHz to 2 MHz Freescale Semiconductor ...
Page 197
... Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected to feed MCGOUT in the current clock mode b) Now, With an RDIV of divide-by-4, a BDIV of divide-by-1, and a VDIV of multiply-by-16, MCGOUT = [(4 MHz / 4) × 16 MHz, and the bus frequency is MCGOUT / MHz Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 197 ...
Page 198
... Figure 12-9. Flowchart of FEI to PEE Mode Transition using a 4 MHz Crystal 198 BLPE MODE ? NO MCGC2 = $36 YES NO YES NO YES NO YES MC9S08JM16 Series Data Sheet, Rev (LP=1) YES ( CHECK NO PLLST = 1? YES CHECK NO LOCK = 1? YES MCGC1 = $10 NO CHECK CLKST = %11? YES CONTINUE IN PEE MODE Freescale Semiconductor ...
Page 199
... Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been selected as the reference clock source c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference clock is selected to feed MCGOUT Freescale Semiconductor MC9S08JM16 Series Data Sheet, Rev. 2 Multi-Purpose Clock Generator (S08MCGV1) 199 ...
Page 200
... YES MCGC2 = $36 ( Figure 12-10. Flowchart of PEE to BLPI Mode Transition using a 4 MHz Crystal 200 CHECK PLLST = 0? NO OPTIONAL: CHECK LOCK = 1? NO MCGC1 = $44 CHECK IREFST = 0? CHECK NO CLKST = %01? MCGC2 = $08 CONTINUE IN BLPI MODE MC9S08JM16 Series Data Sheet, Rev YES NO YES NO YES NO YES Freescale Semiconductor ...