MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet

IC MCU 1.5K FLASH 8MHZ 20-DIP

MCR908JK1ECPE

Manufacturer Part Number
MCR908JK1ECPE
Description
IC MCU 1.5K FLASH 8MHZ 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCR908JK1ECPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
14
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
HC08JK
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCR908JK1ECPE
Manufacturer:
Freescale Semiconductor
Quantity:
135
MC68HC908JL3/JK3E/JK1E
MC68HRC908JL3/JK3E/JK1E
MC68HLC908JL3/JK3E/JK1E
MC68HC903KL3E/KK3E
MC68HC08JL3E/JK3E
MC68HRC08JL3E/JK3E
Data Sheet
M68HC08
Microcontrollers
MC68HC908JL3E
Rev. 4
10/2006
freescale.com

Related parts for MCR908JK1ECPE

MCR908JK1ECPE Summary of contents

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MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet M68HC08 Microcontrollers MC68HC908JL3E Rev. 4 10/2006 freescale.com ...

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...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. ...

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... Updated to reflect the correct RAM location ($80) to — Added note regarding 20-pin devices. — Updated for clarity. — Updated package drawings to MC68HC908JL3E Family Data Sheet, Rev. 4 Page Number( — Added note to definition 89 103 132 147 159–166 167–170 153–224 76, 77 — Freescale Semiconductor ...

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... Chapter 13 Computer Operating Properly (COP 123 Chapter 14 Low Voltage Inhibit (LVI 127 Chapter 15 Break Module (BREAK 129 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 17 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 18 Ordering Information 157 Appendix A MC68HLC908JL3E/JK3E/JK1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Appendix B MC68H(R)C08JL3E/JK3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Appendix C MC68HC908KL3E/KK3E 175 Freescale Semiconductor MC68HC908JL3E Family Data Sheet, Rev ...

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... List of Chapters 6 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... Configuration Register 1 (CONFIG1 3.4 Configuration Register 2 (CONFIG2 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 Features 4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Configuration Registers (CONFIG) Chapter 4 Central Processor Unit (CPU) MC68HC908JL3E Family Data Sheet, Rev ...

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... Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.7.1 Break Status Register (BSR 5.7.2 Reset Status Register (RSR 5.7.3 Break Flag Control Register (BFCR Chapter 5 System Integration Module (SIM) MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.4.4 Pulse Width Modulation (PWM 8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Freescale Semiconductor Chapter 6 Oscillator (OSC) Chapter 7 Monitor ROM (MON) Chapter 8 Timer Interface Module (TIM) MC68HC908JL3E Family Data Sheet, Rev ...

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... Data Direction Register A (DDRA 106 10.2.3 Port A Input Pull-up Enable Register (PTAPUE 107 10.3 Port 108 10.3.1 Port B Data Register (PTB 108 10.3.2 Data Direction Register B (DDRB 108 10 Chapter 9 Analog-to-Digital Converter (ADC) Chapter 10 Input/Output (I/O) Ports MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... COPRS (COP Rate Select 125 13.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Freescale Semiconductor Chapter 11 External Interrupt (IRQ) Chapter 12 Keyboard Interrupt Module (KBI) Chapter 13 Computer Operating Properly (COP) MC68HC908JL3E Family Data Sheet, Rev ...

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... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 16.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 16.9 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 16.10 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 16.11 Typical Supply Currents 143 12 Chapter 14 Low Voltage Inhibit (LVI) Chapter 15 Break Module (BREAK) Chapter 16 Electrical Specifications MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... B.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 B.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 B.7.1 DC Electrical Characteristics 170 B.7.2 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 B.7.3 Memory Characteristics 172 B.8 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Freescale Semiconductor Chapter 17 Mechanical Specifications Chapter 18 Ordering Information Appendix A MC68HLC908JL3E/JK3E/JK1E Appendix B MC68H(R)C08JL3E/JK3E MC68HC908JL3E Family Data Sheet, Rev ...

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... Table of Contents C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 C.5 Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 C.6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 14 Appendix C MC68HC908KL3E/KK3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... ADC-less 1. Low-voltage Flash devices are documented in 2. ROM devices are documented in 3. Flash, ADC-less devices are documented in All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E and MC68H(R)C908JK1E, unless otherwise stated. Freescale Semiconductor Table Oscillator ADC Memory Option 4,096 bytes Flash ...

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... PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H(R)C908JL3E • 20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3E/JK1E 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the Flash difficult for unauthorized users. 16 (1) feature MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... OSC2 MC68HRC908JL3E/JK3E/JK1E RC OSCILLATOR SYSTEM INTEGRATION * RST MODULE EXTERNAL INTERRUPT * IRQ MODULE VDD POWER VSS ADC REFERENCE Freescale Semiconductor INTERNAL BUS KEYBOARD INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE 2-CHANNEL TIMER INTERFACE MODULE BREAK MODULE COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE ...

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... PTD4/TCH0 18 3 PTD5/TCH1 Pins not available on 20-pin packages 17 4 PTD2/ADC9 5 16 PTD3/ADC8 15 6 PTB0/ADC0 7 14 PTB1/ADC1 8 13 PTB2/ADC2 12 9 PTB3/ADC3 10 11 PTB4/ADC4 Internal pads are unconnected. MC68HC908JL3E Family Data Sheet, Rev. 4 PTA0/KBI0 PTD0/ADC11 PTA1/KBI1 PTD1/ADC10 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 Freescale Semiconductor ...

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... NC NC OSC1 OSC2/RCCLK/PTA6/KBI6 PTA1/KBI1 PTA2/KBI2 PTA3KBI3 PTB7/ADC7 NC NC NC: No connection Figure 1-4. 48-Pin LQFP Pin Assignment Freescale Semiconductor MC68H(R)C908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Pin Assignments PTD2/ADC9 32 PTA4/KBI4 PTD3/ADC8 PTB0/ADC0 28 PTB1/ADC1 27 PTD1/ADC10 ...

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... PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1. 20 Table 1-2. Table 1-2. Pin Functions PIN DESCRIPTION NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 IN/OUT VOLTAGE LEVEL Out Input DD TST Input DD TST In Analog Out Analog V In/Out DD V In/Out In/Out DD In Analog V In/Out DD Input Analog V In/Out In/Out DD Freescale Semiconductor ...

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... Monitor ROM The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. Chapter 7 Monitor ROM MC68HC908JL3E Family Data Sheet, Rev ...

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... BYTES RESERVED 64 BYTES RAM 128 BYTES 512 BYTES RESERVED RESERVED RESERVED RESERVED 448 BYTES 48 BYTES Figure 2-1. Memory Map MC68HC908JL3E Family Data Sheet, Rev. 4 $0100 UNIMPLEMENTED ↓ 62,720 BYTES $F5FF FLASH MEMORY $F600 ↓ MC68H(R)C908JK1E 1,536 BYTES $FBFF Freescale Semiconductor ...

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... Write: $000C Read: Port A Input Pull-up Enable $000D Write: Register (PTAPUE) Reset: $000E Read: ↓ Write: Unimplemented $0019 Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset PTD7 ...

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... KBIE2 KBIE1 KBIE0 IRQF 0 IMASK MODE ACK LVIT0 SSREC STOP COPD PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 R = Reserved Freescale Semiconductor ...

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... Reset Status Register $FE01 Write: (RSR) POR: Read: $FE02 Reserved Write: Read: Break Flag Control $FE03 Write: Register (BFCR) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit7 Bit6 Bit5 Bit4 Indeterminate after reset CH1F 0 CH1IE MS1A 0 0 ...

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... Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented MC68HC908JL3E Family Data Sheet, Rev Bit 0 0 IF1 IF15 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Reserved Freescale Semiconductor ...

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... RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. For M6805 compatibility, the H register is not stacked. Freescale Semiconductor Table 2-1. Vector Addresses INT Flag Address $FFD0 ↓ ...

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... BPR7 BPR6 BPR5 Unimplemented Figure 2-3. Flash I/O Register Summary NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 Memory Address Range $EC00—$FBFF $EC00—$FBFF $F600—$FBFF HVEN MASS ERASE BPR4 BPR3 BPR2 BPR1 (1) Freescale Semiconductor Bit 0 PGM 0 BPR0 0 ...

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... Erase operation selected 0 = Erase operation not selected PGM — Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set the same time Program operation selected 0 = Program operation not selected Freescale Semiconductor ...

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... Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 30 NOTE NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... FLBPR determines the range of the Flash memory which protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the Flash memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. Freescale Semiconductor (Figure 2-5 shows a flowchart of the programming ...

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... Write data to the Flash address to be programmed 7 Wait for a time, t Completed programming this row? N MC68HC908JL3E Family Data Sheet, Rev. 4 nvs pgs PROG Y 9 Clear PGM bit 10 Wait for a time, t nvh 11 Clear HVEN bit 12 Wait for a time, t rcv End of Programming Freescale Semiconductor ...

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... Note: The end address of the protected range is always $FFFF. Freescale Semiconductor BPR6 BPR5 BPR4 BPR3 16-bit memory address Start of Address of Protect Range The entire Flash memory is protected ...

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... Memory 34 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... Configuration Register 1 (CONFIG1) Address: $001F Bit 7 Read: COPRS Write: Reset Figure 3-1. Configuration Register 1 (CONFIG1) COPRS — COP reset period selection bit 1 = COP reset cycle is 8176 × 2OSCOUT 0 = COP reset cycle is 262,128 × 2OSCOUT Freescale Semiconductor NOTE and Figure 3- LVID R 0 ...

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... LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in 36 NOTE Chapter 13 Computer Operating Properly LVIT1 LVIT0 Not Not 0 0 affected affected Reserved Chapter 14 Low Voltage Inhibit (LVI) MC68HC908JL3E Family Data Sheet, Rev. 4 (COP).) 2 1 Bit Freescale Semiconductor ...

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... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908JL3E Family Data Sheet, Rev ...

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... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers Unaffected by reset Figure 4-2. Accumulator ( Figure 4-3. Index Register (H:X) MC68HC908JL3E Family Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...

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... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

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... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908JL3E Family Data Sheet, Rev Bit Freescale Semiconductor ...

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... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908JL3E Family Data Sheet, Rev. 4 Arithmetic/Logic Unit (ALU) ...

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... REL 27 – – – – – – REL – – – – – – REL 92 – – – – – – REL 28 – – – – – – REL 29 – – – – – – REL 22 Freescale Semiconductor ...

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... CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ⊕ ...

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... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

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... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

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... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...

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... M Memory location N Negative bit 4.8 Opcode Map See Table 4-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

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... Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor is a summary of the SIM I/O registers. The SIM is a system state Table 5-1. Signal Name Conventions Description MC68HC908JL3E Family Data Sheet, Rev ...

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... OSCILLATOR) OSCOUT (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILOP ILAD MODRST LVI Reserved Freescale Semiconductor Bit ...

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... In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Freescale Semiconductor Bit 7 6 ...

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... Counter), but an external reset does not. Each of Table 5-2. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ( Figure 5-4. External Reset Timing MC68HC908JL3E Family Data Sheet, Rev. 4 5.7 SIM Registers.) Table 5-2 for details. VECT H VECT L Freescale Semiconductor ...

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... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. Freescale Semiconductor RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 5-5. Internal Reset Timing ...

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... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources CYCLES CYCLES Figure 5-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908JL3E Family Data Sheet, Rev. 4 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...

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... Break interrupts 5.5.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 5-8 flow charts the handling of system interrupts. Freescale Semiconductor 5.6.2 Stop Mode 5.3.2 Active Resets from Internal Sources MC68HC908JL3E Family Data Sheet, Rev. 4 SIM Counter ...

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... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO Figure 5-8. Interrupt Processing MC68HC908JL3E Family Data Sheet, Rev. 4 STACK CPU REGISTERS. SET I BIT. EXECUTE INSTRUCTION. Freescale Semiconductor ...

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... Figure 5-11 demonstrates what happens when two interrupts are pending interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. Freescale Semiconductor shows interrupt recovery timing. SP – – – – – ...

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... The interrupt status registers can be useful for debugging. 58 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 BACKGROUND ROUTINE Table 5-3 summarizes the Freescale Semiconductor ...

Page 59

... No interrupt request present Bit and 7 — Always read 0 5.5.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 Read: IF14 Write: R Reset Reserved Figure 5-13. Interrupt Status Register 2 (INT2) Freescale Semiconductor Table 5-3. Interrupt Sources Flag — — IRQF CH0F CH1F TOF KEYF COCO ...

Page 60

... Upon leaving break mode, execution of the second step will clear the flag as normal (BREAK).) The SIM puts the CPU into the break MC68HC908JL3E Family Data Sheet, Rev. 4 Table 5- Bit IF15 Table 5-3. Freescale Semiconductor ...

Page 61

... Figure 5-16 and Figure 5-17 show the timing for WAIT recovery. IAB IDB $A6 EXITSTOPWAIT NOTE: EXITSTOPWAIT = Figure 5-16. Wait Recovery from Interrupt or Break Freescale Semiconductor WAIT ADDR + 1 SAME NEXT OPCODE Figure 5-15. Wait Mode Entry Timing $6E0B $6E0C $00FF $00FE $A6 $A6 ...

Page 62

... Cycles Cycles $6E0B $A6 $A6 NOTE Figure 5-18 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 5-18. Stop Mode Entry Timing MC68HC908JL3E Family Data Sheet, Rev. 4 RST VCT H RST VCT L shows stop mode entry timing. SAME SAME SAME Freescale Semiconductor ...

Page 63

... SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt Freescale Semiconductor STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 5-4 shows the mapping of these registers ...

Page 64

... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR PIN COP ILOP ILAD MC68HC908JL3E Family Data Sheet, Rev Bit 0 MODRST LVI Freescale Semiconductor ...

Page 65

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...

Page 66

... System Integration Module (SIM) 66 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 67

... In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • C EXT • R EXT The RC connection is shown in Freescale Semiconductor Figure 6-2. MC68HC908JL3E Family Data Sheet, Rev ...

Page 68

... See Chapter 16 Electrical Specifications value requirements 2OSCOUT Ext-RC RCCLK Oscillator 0 1 OSC1 PTA6/RCCLK (OSC2) See Chapter 16 Electrical Specifications C EXT value requirements. MC68HC908JL3E Family Data Sheet, Rev SIM for component To SIM To SIM OSCOUT ÷ 2 PTA6 PTA6 I/O PTA6EN for component Freescale Semiconductor ...

Page 69

... The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency. Freescale Semiconductor Oscillator X-tal ...

Page 70

... Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT. 6.6 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state. 70 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 71

... PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the Flash difficult for unauthorized users. Freescale Semiconductor , as long as vector addresses $FFFE and $FFFF are TST (1) ...

Page 72

... TST Figure 7-1. Monitor Mode Circuit MC68HC908JL3E Family Data Sheet, Rev. 4 0.1 μF OSC1 V DD OSC2 0.1 μF OSC1 OSC2 SW1 (SEE NOTE 1) 8 SW2 Freescale Semiconductor RST H(R)C908JL3E H(R)C908JK3E H(R)C908JK1E OSC1 OSC2 IRQ PTB0 PTB1 PTB3 PTB2 ...

Page 73

... V is applied to IRQ. In this event, the OSCOUT frequency is equal to the TST 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. Freescale Semiconductor OSC1 Frequency 4.9152MHz ...

Page 74

... B pin requirements and conditions, DD POR RESET NO NORMAL USER IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR CODE NO POR TRIGGERED? YES MC68HC908JL3E Family Data Sheet, Rev applied to either the IRQ TST MODE 7.4 Security.) After the Freescale Semiconductor ...

Page 75

... The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ = V pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Monitor Mode Entry By: IRQ = V TST Blank reset vector, IRQ = V DD Freescale Semiconductor Functions Reset Reset Break Vector Vector Vector High Low ...

Page 76

... Figure 7-5. Read Transaction TWO-STOP-BIT DELAY BEFORE ZERO ECHO Figure 7-6. Break Transaction MC68HC908JL3E Family Data Sheet, Rev. 4 NEXT START STOP BIT BIT 7 BIT NEXT START BIT 6 BIT 7 STOP BIT BIT STOP NEXT BIT 6 BIT 7 BIT START BIT ADDR. LOW DATA RESULT Freescale Semiconductor ...

Page 77

... Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ECHO Freescale Semiconductor ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. HIGH ADDR. LOW ADDR. LOW MC68HC908JL3E Family Data Sheet, Rev. 4 Functional Description ADDR. LOW DATA RESULT ...

Page 78

... Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE ECHO A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. 78 DATA DATA RESULT DATA DATA NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 79

... Flash locations and execute code from Flash. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Freescale Semiconductor SP HIGH SP LOW RESULT ...

Page 80

... RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). 80 4096 + 32 OSCXCLK CYCLES 24 BUS CYCLES Figure 7-7. Monitor Mode Entry Timing NOTE MC68HC908JL3E Family Data Sheet, Rev Freescale Semiconductor ...

Page 81

... The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in Table 8-1. The generic pin name appear in the text that follows. TIM Generic Pin Names: Full TIM Pin Names: Freescale Semiconductor Table 8-1. Pin Name Conventions TCH0 PTD4/TCH0 MC68HC908JL3E Family Data Sheet, Rev. 4 ...

Page 82

... ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 8-1. TIM Block Diagram MC68HC908JL3E Family Data Sheet, Rev. 4 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX TCH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX TCH1 LOGIC INTERRUPT LOGIC CH1IE Freescale Semiconductor ...

Page 83

... TIM Channel 0 Register High $0026 (TCH0H) TIM Channel 0 Register Low $0027 (TCH0L) TIM Channel 1 Status and $0028 Control Register (TSC1) TIM Channel 1 Register High $0029 (TCH1H) TIM Channel 1 Register Low $002A (TCH1L) Freescale Semiconductor Bit Read: TOF TOIE TSTOP Write: 0 Reset Read: ...

Page 84

... The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers ( that 84 MC68HC908JL3E Family Data Sheet, Rev. 4 8.4.3 Freescale Semiconductor ...

Page 85

... The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. Freescale Semiconductor NOTE OVERFLOW PERIOD ...

Page 86

... User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 86 NOTE NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 8.4.4 Pulse Width Freescale Semiconductor ...

Page 87

... The result duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 8.9.4 TIM Channel Status and Control Registers Freescale Semiconductor Table 8-3.) NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 ...

Page 88

... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at zero. After the break, doing the second step clears the status bit. 88 5.7.3 Break Flag Control Register MC68HC908JL3E Family Data Sheet, Rev. 4 (BFCR).) Freescale Semiconductor ...

Page 89

... TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Freescale Semiconductor ...

Page 90

... Table 8-2. Prescaler Selection TIM Clock Source 0 Internal Bus Clock ÷ Internal Bus Clock ÷ Internal Bus Clock ÷ Internal Bus Clock ÷ Internal Bus Clock ÷ Internal Bus Clock ÷ Internal Bus Clock ÷ Not available MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 91

... Address: $0023 Bit 7 Read: Bit15 Write: Reset: 1 Address: $0024 Bit 7 Read: Bit7 Write: Reset: 1 Figure 8-6. TIM Counter Modulo Registers (TMODH:TMODL) Reset the TIM counter before writing to the TIM counter modulo registers. Freescale Semiconductor NOTE TCNTH Bit14 Bit13 Bit12 Bit11 TCNTL 6 5 ...

Page 92

... This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled 92 TSC0 CH0IE MS0B MS0A ELS0B TSC1 CH1IE MS1A ELS1B MC68HC908JL3E Family Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...

Page 93

... Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. Freescale Semiconductor Table 8-3. NOTE ELSxA Mode 0 Pin under Port Control; Initial Output Level High Output Preset 0 Pin under Port Control; Initial Output Level Low ...

Page 94

... The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW TCHx COMPARE CHxMAX 94 NOTE shows, the CHxMAX bit takes effect in the cycle after it is set or OVERFLOW OVERFLOW PERIOD OUTPUT OUTPUT OUTPUT COMPARE COMPARE Figure 8-8. CHxMAX Latency MC68HC908JL3E Family Data Sheet, Rev. 4 OVERFLOW OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...

Page 95

... Bit 7 Read: Bit7 Write: Reset: Address: $0029 Bit 7 Read: Bit15 Write: Reset: Address: $02A Bit 7 Read: Bit7 Write: Reset: Figure 8-9. TIM Channel Registers (TCH0H/L:TCH1H/L) Freescale Semiconductor TCH0H Bit14 Bit13 Bit12 Bit11 Indeterminate after reset TCH0L Bit6 Bit5 Bit4 Bit3 Indeterminate after reset ...

Page 96

... Timer Interface Module (TIM) 96 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 97

... An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Freescale Semiconductor Bit ...

Page 98

... DDRBx/DDRDx RESET PTBx/PTDx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 9-2. ADC Block Diagram MC68HC908JL3E Family Data Sheet, Rev. 4 DISABLE ADCx DISABLE ADC CHANNEL x CHANNEL SELECT ( CHANNELS) Freescale Semiconductor ADCH[4:0] ...

Page 99

... MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to 1’s before executing the WAIT instruction. Freescale Semiconductor , the ADC converts the signal to $FF (full scale). If the input DD ...

Page 100

... When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit ADC interrupt enabled 0 = ADC interrupt disabled 100 AIEN ADCO ADCH4 ADCH3 Unimplemented MC68HC908JL3E Family Data Sheet, Rev Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...

Page 101

... If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications. Freescale Semiconductor NOTE Table 9-1. MUX Channel Select ...

Page 102

... Table 9-2. ADC Clock Divide Ratio ADIV0 0 0 ADC Input Clock ÷ ADC Input Clock ÷ ADC Input Clock ÷ ADC Input Clock ÷ ADC Input Clock ÷ 16 MC68HC908JL3E Family Data Sheet, Rev Bit 0 AD2 AD1 AD0 2 1 Bit ADC Clock Rate Freescale Semiconductor ...

Page 103

... Reset: Read: Data Direction Register A $0004 Write: (DDRA) Reset: Read: Data Direction Register B $0005 Write: (DDRB) Reset: Read: Data Direction Register D $0007 Write: (DDRD) Reset: Freescale Semiconductor NOTE Bit PTA6 PTA5 PTB7 PTB6 PTB5 PTD7 PTD6 PTD5 0 DDRA6 DDRA5 DDRA4 0 0 ...

Page 104

... KBIE1 PTA1/KBI1 KBIE2 PTA2/KBI2 KBIE3 PTA3/KBI3 KBIE4 PTA4/KBI4 KBIE5 PTA5/KBI5 PTA6EN RCCLK/PTA6/KBI6 KBIE6 PTB0/ADC0 PTB1/ADC1 PTB2/ADC2 PTB3/ADC3 ADCH[4:0] PTB4/ADC4 PTB5/ADC5 PTB6/ADC6 PTB7/ADC7 PTD0/ADC11 PTD1/ADC10 ADCH[4:0] PTD2/ADC9 PTD3/ADC8 ELS0B:ELS0A PTD4/TCH0 ELS1B:ELS1A PTD5/TCH1 — PTD6 — PTD7 Freescale Semiconductor Bit 0 PTDPU6 0 PTAPUE0 0 (1) ...

Page 105

... A. Reset has no effect on port A data. KBI[6:0] — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE[6:0], in the keyboard interrupt control register (KBIER) enable the port A pins as external interrupt pins, (see Freescale Semiconductor (KBI)). Each port A pin also has software configurable NOTE 6 ...

Page 106

... The data latch can always be written, regardless of the state of its data direction bit. 106 DDRA6 DDRA5 DDRA4 DDRA3 NOTE DDRAx PTAx Figure 10-4. Port A I/O Circuit MC68HC908JL3E Family Data Sheet, Rev Bit 0 DDRA2 DDRA1 DDRA0 PTAPUEx 30k PTAx To Keyboard Interrupt Circuit Freescale Semiconductor ...

Page 107

... PTAPUE Bit PTA Bit Bit Don’t care. 2. I/O pin pulled internal pull-up Writing affects data register, but does not affect input. 4. Hi-Z = High Impedance. Freescale Semiconductor PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 Table 10-2. Port A Pin Functions Accesses to DDRA I/O Pin Mode ...

Page 108

... Unaffected by reset ADC6 AD4C5 ADC4 Figure 10-6. Port B Data Register (PTB DDRB6 DDRB5 DDRB4 DDRB3 NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 (ADC Bit 0 PTB3 PTB2 PTB1 PTB0 ADC3 ADC2 ADC2 ADC0 Chapter 9 Analog-to-Digital Converter 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...

Page 109

... don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. Freescale Semiconductor DDRBx PTBx Figure 10-8. Port B I/O Circuit summarizes the operation of the port B pins. Table 10-3. Port B Pin Functions Accesses to DDRB I/O Pin Mode ...

Page 110

... TCH0 25mA sink (Slow Edge) 5k pull-up = Unimplemented Figure 10-9. Port D Data Register (PTD) Chapter 8 Timer Interface Module MC68HC908JL3E Family Data Sheet, Rev Bit 0 PTD3 PTD2 PTD1 PTD0 LED LED (Sink) (Sink) ADC8 ADC9 ADC10 ADC11 Chapter 9 Analog-to-Digital Converter (TIM). Freescale Semiconductor ...

Page 111

... READ PTD ($0003) When DDRDx reading address $0003 reads the PTDx data latch. When DDRDx reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-4 Freescale Semiconductor ...

Page 112

... Disable 5kΩ pull-up 112 Table 10-4. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (1) (2) Input, Hi-Z DDRD[7:0] Output DDRD[7: SLOWD7 MC68HC908JL3E Family Data Sheet, Rev. 4 Accesses to PTD Read Write (3) Pin PTD[7:0] Pin PTD[7: Bit 0 SLOWD6 PTDPU7 PTDPU6 Freescale Semiconductor ...

Page 113

... When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic one Freescale Semiconductor MC68HC908JL3E Family Data Sheet, Rev. 4 Figure 11-1 shows the 113 ...

Page 114

... IRQ FF IMASK MODE Figure 11-1. IRQ Module Block Diagram Bit Unimplemented MC68HC908JL3E Family Data Sheet, Rev. 4 5.5 Exception IRQF SYNCHRO- NIZER HIGH VOLTAGE DETECT IRQF 0 IMASK ACK Freescale Semiconductor TO CPU FOR BIL/BIH INSTRUCTIONS IRQ INTERRUPT REQUEST TO MODE SELECT LOGIC Bit 0 MODE 0 ...

Page 115

... To protect the latches during the break state, write a zero to the BCFE bit. With BCFE at zero (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. Freescale Semiconductor NOTE NOTE is connected to the IRQ pin ...

Page 116

... Figure 11-4. Configuration Register 2 (CONFIG2) IRQPUD — IRQ Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and V 116 IRQF Unimplemented LVIT1 LVIT0 0 0 Not affected Not affected Reserved MC68HC908JL3E Family Data Sheet, Rev Bit 0 IMASK MODE ACK Bit Freescale Semiconductor ...

Page 117

... The seven keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 12-1. The generic pin name appear in the text that follows. KBI Generic Pin Name KBI0–KBI5 KBI6 1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option). Freescale Semiconductor Bit ...

Page 118

... Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin the keyboard interrupt remains set. 118 V DD CLR KEYBOARD INTERRUPT FF MODEK (PTAPUE)). A logic 0 applied to an enabled keyboard MC68HC908JL3E Family Data Sheet, Rev. 4 INTERNAL BUS VECTOR FETCH DECODER ACKK KEYF RESET SYNCHRONIZER IMASKK Freescale Semiconductor KEYBOARD INTERRUPT REQUEST ...

Page 119

... Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 12.5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: • Keyboard status and control register • Keyboard interrupt enable register Freescale Semiconductor NOTE MC68HC908JL3E Family Data Sheet, Rev. 4 Keyboard Interrupt Registers 119 ...

Page 120

... This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-A. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 120 KEYF Unimplemented MC68HC908JL3E Family Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...

Page 121

... If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. Freescale Semiconductor ...

Page 122

... Keyboard Interrupt Module (KBI) 122 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 123

... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) NOTE: See Chapter 5 System Integration Module (SIM) Freescale Semiconductor SIM 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...

Page 124

... COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). (See Chapter 3 Configuration Registers 124 NOTE (RSR).). NOTE Figure 13-1. 13.4 COP Control (CONFIG).) MC68HC908JL3E Family Data Sheet, Rev. 4 Register) clears the COP Freescale Semiconductor ...

Page 125

... Figure 13-3. COP Control Register (COPCTL) 13.5 Interrupts The COP does not generate CPU interrupt requests. 13.6 Monitor Mode The COP is disabled in monitor mode when V 13.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Freescale Semiconductor ...

Page 126

... COP timeout period after entering or exiting stop mode. 13.8 COP Module During Break Mode The COP is disabled during a break interrupt when V 126 is present on the RST pin. TST MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 127

... The LVI module generates one output signal: LVI Reset — an reset signal will be generated to reset the CPU when V point LOW DETECTOR LVIT1 LVIT0 Freescale Semiconductor voltage falls to the LVI trip (LVI DD LVID > LVI = 0 TRIP DD < LVI = 1 TRIP DD Figure 14-1. LVI Module Block Diagram MC68HC908JL3E Family Data Sheet, Rev ...

Page 128

... LVI module will come into action. LVIT1 and LVIT0 DD (1) LVIT0 Trip Voltage 0 V (2.4V) LVR3 1 V (2.4V) LVR3 0 V (4.0V) LVR5 1 Reserved for full parameters. MC68HC908JL3E Family Data Sheet, Rev Bit Bit 0 SSREC STOP COPD Comments For V =3V operation DD For V =3V operation DD For V =5V operation DD Freescale Semiconductor ...

Page 129

... CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. structure of the break module. IAB[15:0] Figure 15-1. Break Module Block Diagram Freescale Semiconductor IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR ...

Page 130

... Bit5 Bit4 BRKE BRKA Unimplemented 5.7.3 Break Flag Control Register (BFCR) is present on the RST pin. TST MC68HC908JL3E Family Data Sheet, Rev SBSW See note Bit11 Bit10 Bit9 Bit3 Bit2 Bit1 Reserved and see the Break Interrupts Freescale Semiconductor Bit Bit8 0 Bit0 ...

Page 131

... This read/write status and control bit is set when a break address match occurs. Writing a one to BRKA generates a break interrupt. Clear BRKA by writing a zero to it before exiting the break routine. Reset clears the BRKA bit Break address match break address match Freescale Semiconductor ...

Page 132

... SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt 132 Writing a zero clears SBSW. MC68HC908JL3E Family Data Sheet, Rev Bit Bit Bit Bit Bit 0 SBSW R R (1) Note 0 Freescale Semiconductor ...

Page 133

... If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see zero to it. 15.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 5.7 SIM Registers. Freescale Semiconductor ...

Page 134

... Break Module (BREAK) 134 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 135

... For proper operation recommended that V ≤ (V range unused inputs are connected to an appropriate logic voltage level (for example, either V Freescale Semiconductor NOTE and Table 16-1. Absolute Maximum Ratings (1) and NOTE ...

Page 136

... MC68HC908JL3E Family Data Sheet, Rev. 4 Value – +125 – +85 5 ±10% 3 ±10% Value User determined × I/O + 273 °C) K/( 273 ° × θ × θ With this value Freescale Semiconductor Unit °C V Unit °C/W °C/W °C/W °C/W °C W/°C °C and T J ...

Page 137

... MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) (6) POR rearm voltage (7) POR rise time ramp rate Monitor mode entry voltage (8) Pullup resistors PTD6, PTD7 RST, IRQ, PTA0–PTA6 Freescale Semiconductor (1) Symbol ...

Page 138

... Table 16-5. Control Timing (5V) (1) Symbol = timing shown with respect to 20 MC68HC908JL3E Family Data Sheet, Rev. 4 (2) Min Max Typ 3.6 4.0 4.4 = 4MHz). All inputs 0.2V from rail Min Max f — 750 — IRL and 70 unless otherwise DD SS Freescale Semiconductor Unit V Unit MHz ns ...

Page 139

... RC oscillator external R RC oscillator external more than 10% duty cycle deviation from 50%. 2. Consult crystal vendor data sheet. 3. Not required for high frequency crystals Figure 16-1. RC vs. Frequency (5V @25°C) Freescale Semiconductor Symbol Min f — OSCXCLK f 2 RCCLK f dc OSCXCLK C — — ...

Page 140

... V — 8.5 DD 1.8 3.3 4 Table continued on next page Freescale Semiconductor Unit μA μA μA μ V/ms V kΩ kΩ ...

Page 141

... DD SS noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. 3. Minimum pulse width reset is guaranteed to be recognized possible for a smaller pulse width to cause a reset. Freescale Semiconductor Symbol V LVR3 = unless otherwise noted. ...

Page 142

... EXT 3V @ 25° RESISTOR, R (kΩ) EXT MC68HC908JL3E Family Data Sheet, Rev. 4 Typ Max Unit 8 16 MHz 8 12 MHz — 16 MHz — — 2 × C — × C — MΩ — — — See Figure 16-2 10 — pF MCU OSC1 EXT EXT 50 Freescale Semiconductor ...

Page 143

... Typical Supply Currents Figure 16-3. Typical Operating Figure 16-4. Typical Operating Figure 16-5. Typical Wait Mode I Freescale Semiconductor MC68HC908JL3E/JK3E/JK1E (MHz) OP BUS (MC68HC908JL3E/JK3E/JK1E), DD with All Modules Turned On (25°C) MC68HRC908JL3E/JK3E/JK1E 5 (MHz) OP BUS (MC68HRC908JL3E/JK3E/JK1E), DD with All Modules Turned On (25°C) MC68HC908JL3E/JK3E/JK1E 5 ...

Page 144

... ADI ± 1 — — MC68HC908JL3E Family Data Sheet, Rev Unit Comments V max Bits LSB Includes quantization t = 1/f AIC ADIC MHz only at 1 MHz cycles AIC t cycles AIC t cycles AIC Hex Hex IN pF Not tested μA Freescale Semiconductor , tested SS DD ...

Page 145

... The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 8. The Flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. Freescale Semiconductor Table 16-11. Memory Characteristics Symbol ...

Page 146

... Electrical Specifications 146 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

Page 147

... The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office. 17.2 Package Dimensions Refer to the following pages for detailed package dimensions. –A– –T– SEATING PLANE Freescale Semiconductor 0.25 (0.010) ...

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... Mechanical Specifications 156 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... MC68HRC98JK3EMDW MC68HC908JK1ECP MC68HC908JK1EMP MC68HC908JK1ECDW MC68HC908JK1EMDW MC68HRC98JK1ECP MC68HRC98JK1EMP MC68HRC98JK1ECDW MC68HRC98JK1EMDW Temperature –40°C to +85°C Package PDIP Freescale Semiconductor Table 18-1. MC Order Numbers Oscillator Type Flash Memory Crystal oscillator 4096 Bytes RC oscillator Crystal oscillator 4096 Bytes RC oscillator Crystal oscillator 4096 Bytes RC oscillator ...

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... Ordering Information 158 MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... Electrical specifications for low-voltage devices are given in the following tables. A.5.1 Functional Operating Range Characteristic Operating temperature range Operating voltage range Operating voltage for Flash memory program and erase operations Freescale Semiconductor of 2.2V 2.7V. DD Table A-1. Operating Range MC68HC908JL3E Family Data Sheet, Rev. 4 ...

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... V V — — 2 3.5 — 1 1.5 — ± 10 — — ± 1 — — — — 12 — — — 100 0.02 — — 1.8 3.3 4 RST must be driven low externally until minimum Freescale Semiconductor Unit μA μA μ V/ms kΩ kΩ ...

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... Crystal fixed capacitance (2) Crystal tuning capacitance Feedback bias resistor (2), (3) Series resistor 1. No more than 10% duty cycle deviation from 50% 2. Consult crystal vendor data sheet 3. Not Required for high frequency crystals Freescale Semiconductor Table A-3. Control Timing (1) Symbol timing shown with respect to 20 ...

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... ADI ± 1 — — MC68HC908JL3E Family Data Sheet, Rev. 4 Unit Comments V max) V Bits LSB Includes quantization t = 1/f AIC ADIC MHz only at 1 MHz V t cycles AIC t cycles AIC t cycles AIC Hex Hex IN pF Not tested μA Freescale Semiconductor , tested SS DD ...

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... The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 8. The Flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. Freescale Semiconductor Table A-6. Memory Characteristics (Min), there is no erase-disturb, but it reduces the endurance of the Flash mem- ...

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... DW = Small outline integrated circuit package (SOIC Low-Profile Quad Flat Pack (LQFP) 164 Oscillator Type Flash Memory Crystal oscillator 4096 Bytes Crystal oscillator 4096 Bytes Crystal oscillator 4096 Bytes Crystal oscillator 1536 Bytes MC68HC908JL3E Family Data Sheet, Rev. 4 Package 48-pin LQFP 28-pin package 20-pin package Freescale Semiconductor ...

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... Registers at $FE08 and $FE09 Monitor ROM ($FC00–$FDFF and $FE10–$FFCF) B.2 MCU Block Diagram Figure B-1 shows the block diagram of the MC68H(R)C08JL3E/JK3E. Freescale Semiconductor MC68H(R)C08JL3E/JK3E 4,096 bytes ROM 48 bytes ROM Not used; locations are reserved. $FC00–$FDFF: Not used. ...

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... MC68HC908JL3E Family Data Sheet, Rev. 4 ¥ PTA6/KBI6** ‡ PTA5/KBI5** ‡ PTA4/KBI4** ‡ PTA3/KBI3** # ‡ PTA2/KBI2** ‡ PTA1/KBI1** ‡ PTA0/KBI0** PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 †‡ PTD7** †‡ PTD6** PTD5/TCH1 PTD4/TCH0 ‡ PTD3/ADC8 ‡ PTD2/ADC9 PTD1/ADC10 # PTD0/ADC11 Freescale Semiconductor ...

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... Figure B-2. MC68H(R)C08JL3E/JK3E Memory Map Freescale Semiconductor I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 60,160 BYTES ROM MC68H(R)C08JL3E/JK3E 4,096 BYTES MONITOR ROM 512 BYTES BREAK STATUS REGISTER (BSR) ...

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... COP reset cycle is 8176 × 2OSCOUT 0 = COP reset cycle is 262,128 × 2OSCOUT LVID — Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled 168 LVID Unimplemented MC68HC908JL3E Family Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...

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... LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in B.6 Monitor ROM The monitor program (monitor ROM: $FE10–$FFCF) on the MC68H(R)C08JL3E/JK3E is for device testing only. $FC00–$FDFF are unused. Freescale Semiconductor NOTE Chapter 13 Computer Operating Properly 6 5 ...

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... MC68HC908JL3E Family Data Sheet, Rev. 4 (2) Min Max Typ — — 4.3 5 — 5.5 6.5 — 0.8 1.5 — 1.8 5 — 1.8 5 — — 1.8 4.3 4 4MHz). All inputs 0.2V from rail Freescale Semiconductor Unit μA μA μA μA kΩ kΩ ...

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... L 5. Stop I measured with OSC1 grounded; no port pins sourcing current. LVI is disabled and R are measured at V PU1 PU2 B.7.2 5V Oscillator Characteristics Table B-4. Oscillator Component Specifications (5V) Characteristic RC oscillator external R RC oscillator external C Freescale Semiconductor Symbol PU1 R PU2 = unless otherwise noted OSC2. All ports configured as inputs. OSC2 capacitance linearly L = 2MHz) ...

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... C EXT 5V @ 25° RESISTOR, R (kΩ) EXT C EXT 3V @ 25° RESISTOR, R (kΩ) EXT Table B-5. Memory Characteristics MC68HC908JL3E Family Data Sheet, Rev OSC1 EXT OSC1 EXT 50 Symbol Min Max V 1.3 — RDR Freescale Semiconductor MCU C EXT MCU C EXT Unit V ...

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... MC68HRC08JK3ECP MC68HRC08JK3EMP MC68HRC08JK3ECDW MC68HRC08JK3EMDW NOTES –40 °C to +85 ° –40 °C to +125 °C (available for Plastic dual in-line package (PDIP Small outline integrated circuit package (SOIC) Freescale Semiconductor Table B-6. MC Order Numbers Oscillator Type Crystal RC Crystal only) DD MC68HC908JL3E Family Data Sheet, Rev. 4 ...

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... MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor ...

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... C.2 MCU Block Diagram Figure C-1 shows the block diagram of the MC68HC908KL3E/KK3E. C.3 Pin Assignments Figure C-2 and Figure C-3 show the pin assignments for the MC68HC908KL3E/KK3E. Freescale Semiconductor MC68HC908KL3E/KK3E — Not used; locations are reserved. Not used. 20-pin PDIP (MC68HC908KK3E) 20-pin SOIC (MC68HC908KK3E) ...

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... MC68HC908JL3E Family Data Sheet, Rev. 4 ‡ PTA5/KBI5** ‡ PTA4/KBI4** ‡ PTA3/KBI3** # ‡ PTA2/KBI2** ‡ PTA1/KBI1** ‡ PTA0/KBI0** PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 †‡ PTD7** †‡ PTD6** PTD5/TCH1 PTD4/TCH0 ‡ PTD3 ‡ PTD2 PTD1 # PTD0 Freescale Semiconductor ...

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... PTB7 PTB6 PTB5 PTD7 PTD6 MC68HC908KL3E Figure C-2. 28-Pin PDIP/SOIC Pin Assignment IRQ VSS OSC1 OSC2 VDD PTB7 PTB6 PTB5 PTD7 PTD6 MC68HC908KK3E Figure C-3. 20-Pin PDIP/SOIC Pin Assignment Freescale Semiconductor 28 1 RST 2 27 PTA5/KBI5 26 3 PTD4/TCH0 4 25 PTD5/TCH1 24 PTD2 PTA4 ...

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... Bit Figure C-4. Reserved Registers Table C-2. Reserved Vectors INT Flag Address $FFDE Reserved IF15 $FFDF Reserved Operating Temperature –40 to +85 °C MC68HC908JL3E Family Data Sheet, Rev Vector Operating OSC Flash Memory V DD 3V, 5V XTAL 4096 Bytes Freescale Semiconductor Bit ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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