MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet
MCHC908JW32FAE
Specifications of MCHC908JW32FAE
Available stocks
Related parts for MCHC908JW32FAE
MCHC908JW32FAE Summary of contents
Page 1
MC68HC908JW32 Data Sheet M68HC08 Microcontrollers MC68HC908JW32 Rev. 6 3/2009 freescale.com ...
Page 2
...
Page 3
... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006, 2009. All rights reserved. ...
Page 4
... Characteristics, corrected crystal characteristics MC68HC908JW32 Data Sheet, Rev. 6 and V . DDA SSA and DDA connection DDPLL SSA SS connection. DDPLL ) — Reworked for clarity. — Corrected pin numbers 37 through 48 Freescale Semiconductor ...
Page 5
... Chapter 14 External Interrupt (IRQ .185 Chapter 15 Keyboard Interrupt Module (KBI .191 Chapter 16 Computer Operating Properly (COP .197 Chapter 17 Low-Voltage Inhibit (LVI .201 Chapter 18 Break Module (BRK .205 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .221 Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev ...
Page 6
... List of Chapters 6 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 7
... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5.2 FLASH Control Register 2.5.3 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.4 FLASH Mass Erase Operation 2.5.5 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.6 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.5.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Freescale Semiconductor List of Chapters Table of Contents Chapter 1 General Description and and DDPLL SSPLL ...
Page 8
... Crystal Amplifier Output Pin (OSC2 5.4.3 External Filter Capacitor Pin (CGMXFC 5.4.4 Oscillator Output Frequency Signal (CGMXCLK 5.4.5 CGM Reference Clock (CGMRCLK Chapter 3 Configuration Registers (CONFIG) Chapter 4 Central Processor Unit (CPU) Chapter 5 Clock Generator Module (CGM) MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 9
... SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5 Exception Control 6.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.2.1 Interrupt Status Register 6.5.2.2 Interrupt Status Register 6.5.2.3 Interrupt Status Register Freescale Semiconductor Chapter 6 System Integration Module (SIM) MC68HC908JW32 Data Sheet, Rev ...
Page 10
... Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 Chapter 7 Monitor Mode (MON) Chapter 8 Timer Interface Module (TIM) MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 11
... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Freescale Semiconductor Chapter 9 Timebase Module (TBM) Chapter 10 MC68HC908JW32 Data Sheet, Rev ...
Page 12
... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.3 PS2 Clock Generator Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.2 Port 170 12 Chapter 11 USB 2.0 FS Module Chapter 12 PS2 Clock Generator (PS2CLK) Chapter 13 Input/Output (I/O) Ports MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 13
... Keyboard Status and Control Register 194 15.5.2 Keyboard Interrupt Enable Register 195 15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.7 Keyboard Module During Break Interrupts 195 Freescale Semiconductor Chapter 14 External Interrupt (IRQ) Chapter 15 Keyboard Interrupt Module (KBI) MC68HC908JW32 Data Sheet, Rev ...
Page 14
... Flag Protection During Break Interrupts 206 18.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.3.3 TIMI and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14 Chapter 16 Computer Operating Properly (COP) Chapter 17 Low-Voltage Inhibit (LVI) Chapter 18 Break Module (BRK) MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 15
... FLASH Program/Erase Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.12 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.13 5.0V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Ordering Information and Mechanical Specifications 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Freescale Semiconductor Chapter 19 Electrical Specifications Chapter 20 MC68HC908JW32 Data Sheet, Rev ...
Page 16
... Table of Contents 16 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 17
... Low-power design (fully static with stop and wait modes) • Master reset pin with internal pull-up and power-on reset 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH/ROM difficult for unauthorized users. Freescale Semiconductor (1) MC68HC908JW32 Data Sheet, Rev ...
Page 18
... PTA1/KBA1 (3) PTA0/KBA0 (2)(4)(5) PTB7 (2)(4)(5) PTB6 (2)(4) PTB5 (2)(4)(5) PTB4 (2)(4)(5) PTB3 (2)(4)(5) PTB2 (2)(4) PTB1 (2)(4) PTB0 PTC3 PTC2/T1CH1 PTC1/TCLK1 PTC0/T1CH0 (2) PTD7 PTD6 PTD5 PTD4 (2) PTD3 (2) PTD2 PTD1 PTD0 PTE7/SS PTE6/MISO PTE5/MOSI PTE4/SPCLK (2)(4) PTE3/D– (2)(4) PTE2/PS2CLK/D+ Freescale Semiconductor ...
Page 19
... PTC1/TCLK1 2 PTC3 3 PTB7 4 PTB6 5 6 PTB5 PTB4 7 8 PTC0/T1CH0 9 PTE7/SS 10 PTE6/MISO 11 PTE5/MOSI 12 PTE4/SPCLK 13 NC Figure 1-2. 52-Pin LQFP Pin Assignment Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 Pin Assignments V 39 DDPLL 38 CGMXFC 37 V SSPLL 36 REG33V 35 PTE3/D– 34 PTE2/PS2CLK/ SS33 32 PTB3 31 PTB2 30 PTB1 ...
Page 20
... SIM CGMOUT ÷2 CGMVCLK USB Figure 1-4. Clock Tree Diagram MC68HC908JW32 Data Sheet, Rev. 6 PTA7/KBA7 DDPLL 34 CGMXFC 33 V SSPLL REG33V 32 PTE3/D– PTE2/PS2CLK/ SS33 PTB1 28 27 PTB0 26 OSC2 OSC1 Connection TBM TIMER CPU RAM FLASH KBI BREAK PS2CLK Freescale Semiconductor SPI ...
Page 21
... MCU as shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. Freescale Semiconductor GPIO Pad Ring USB CPU ...
Page 22
... The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. 22 MCU 0.1 µ NOTE: Component values shown represent typical applications. Figure 1-6. Power Supply Bypassing and V ) DDPLL SSPLL and V DDPLL MC68HC908JW32 Data Sheet, Rev pins placing it as close to the pins SSPLL ) SS33 Freescale Semiconductor ...
Page 23
... Port E Input/Output (I/O) Pins (PTE7–PTE2) PTE7–PTE2 are special function, bidirectional ports pins. PTE2–PTE3 are shared with USB 2.0 FS module. PTE2 is shared with PS2 clock module. PTE4–PTE7 are shared with SPI module. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 Pin Function ...
Page 24
... General Description 24 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 25
... The 1024 bytes at addresses $FA00–$FDFF and 448 bytes at addresses $FE10–$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See (MON).) Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. MC68HC908JW32 Data Sheet, Rev. 6 ...
Page 26
... FLASH Block Protect Register (FLBPR) Reserved Reserved Break Address High Register (BRKH) Break Address Low Register (BRKL) Break Status and Control Register (BRKSCR) LVI Status Register (LVISR) Monitor ROM 2 448 Bytes FLASH Vectors 48 Bytes Figure 2-1. Memory Map MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 27
... Write: Register (T1SC) Reset: Read: $000B Reserved Write: Read: Timer 1 Counter Register $000C Write: High (T1CNTH) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset ...
Page 28
... Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TBIE TBON R TACK CSEL0 PS2IEN CLKEN PS2EN Reserved U = Unaffected by reset Freescale Semiconductor ...
Page 29
... Data Register 1 Write: (UE0D1) Reset: Read: USB Endpoint 0 $0042 Data Register 2 Write: (UE0D2) Reset: Read: USB Endpoint 0 $0043 Data Register 3 Write: (UE0D3) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit LEDB7 LEDB6 LEDB5 LEDB4 PTD7PD PTD3PD ...
Page 30
... SPRF OVRF MODF ERRIE Unaffected by reset Unimplemented R MC68HC908JW32 Data Sheet, Rev Bit 0 UE0D43_IN UE0D42_IN UE0D41_IN UE0D40_IN UE0D53_IN UE0D52_IN UE0D51_IN UE0D50_IN UE0D63_IN UE0D62_IN UE0D61_IN UE0D60_IN UE0D73_IN UE0D72_IN UE0D71_IN UE0D70_IN CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 Reserved U = Unaffected by reset Freescale Semiconductor ...
Page 31
... Write: (UEP3DSR) Reset: Read: USB EP4 Data Size Register $005C Write: (UEP4DSR) Reset: Read: USB EP 1/2 Base Pointer $005D Register Write: (UEP12BPR) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit USBEN TFC4IE TFC3IE USBCLKEN SETUP SOF ...
Page 32
... MC68HC908JW32 Data Sheet, Rev Bit 0 BASE32 BASE31 BASE30 EP2INT EP1INT PRE1 PRE0 VPR1 VPR0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 VRS3 VRS2 VRS1 VRS0 RDS3 RDS2 RDS1 RDS0 SBSW See note 0 ILAD USB LVI Reserved U = Unaffected by reset Freescale Semiconductor ...
Page 33
... Break Status and Control $FE0E Write: Register (BRKSCR) Reset: Read: LVI Sttatusl Register $FE0F Write: (LVISR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit IF6 IF5 IF4 IF3 IF14 ...
Page 34
... USB Endpoint Vector (Low) $FFFA USB System Vector (High) IF1 $FFFB USB System Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908JW32 Data Sheet, Rev. 6 Vector Freescale Semiconductor ...
Page 35
... Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor NOTE NOTE NOTE NOTE MC68HC908JW32 Data Sheet, Rev ...
Page 36
... Write any data to any FLASH location within the page address range desired. (5 µs). 3. Wait for a time, t nvs 4. Set the HVEN bit. 5. Wait for a time t (20 ms). erase 6. Clear the ERASE bit HVEN MC68HC908JW32 Data Sheet, Rev Bit 0 MASS ERASE PGM Freescale Semiconductor ...
Page 37
... Repeat steps 6 and 7 until all bytes within the row are programmed. 9. Clear the PGM bit. (5 µs). 10. Wait for time, t nvh 11. Clear the HVEN bit. (1 µs), the memory can be accessed in read mode again. 12. After time, t rcv Freescale Semiconductor NOTE NOTE shows a flowchart of the programming algorithm.) MC68HC908JW32 Data Sheet, Rev. 6 FLASH Memory 37 ...
Page 38
... When the memory is protected, the HVEN bit cannot be set in either erase or program operations. The 48 bytes of user interrupt vectors ($FFD0–$FFFF) are always protected, regardless of the value in the FLASH block protect register. A mass erase is required to erase these locations. 38 NOTE NOTE NOTE MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 39
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 ...
Page 40
... Table 2-2 FLASH Block Protect Range Protected Range The entire FLASH memory is protected. $7000 to $FFFF (The entire FLASH memory is protected.) $7200 to $FFFF $7400 to $FFFF and so on... $EE00 to $FFFF The entire FLASH memory is NOT protected. MC68HC908JW32 Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 (1) Freescale Semiconductor ...
Page 41
... Since the various options affect the operation of the MCU recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime. Freescale Semiconductor Bit 7 6 ...
Page 42
... CGMXCLK delay is less than the LVI’s turn-on time and there exists a period in start-up where the LVI is not protecting the MCU LVISTOP LVIRSTD LVIPWRD Unimplemented disabled DD is enabled DD NOTE NOTE MC68HC908JW32 Data Sheet, Rev Bit 0 SSREC STOP COPD Chapter 16 Computer Operating is disabled. DD Freescale Semiconductor ...
Page 43
... URSTD — USB Reset Disable Bit URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers. Instead, it will generate an interrupt request to CPU USB reset generates a interrupt request to CPU 0 = USB reset generates a chip reset Freescale Semiconductor Chapter 16 Computer Operating Properly ...
Page 44
... Configuration Registers (CONFIG) 44 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 45
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev ...
Page 46
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers Unaffected by reset Figure 4-2. Accumulator ( Figure 4-3. Index Register (H:X) MC68HC908JW32 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
Page 47
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 48
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908JW32 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 49
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 Arithmetic/Logic Unit (ALU) ...
Page 50
... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...
Page 51
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 52
... SP1 9E6A ff – – – – ↕ ↕ INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C ↕ – – ↕ ↕ – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 53
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 54
... INH 8E DIR BF dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 ↕ – – ↕ ↕ ↕ IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 55
... M Memory location N Negative bit 4.8 Opcode Map See Table 4-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 56
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 57
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the divided VCO clock, CGMVCLK, divided by three as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 5-1 shows the structure of the CGM. Figure 5 summary of the CGM registers. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev ...
Page 58
... AUTO ACQ PLLIE PLLF PRE[1: CGMPCLK FREQUENCY DIVIDER Figure 5-1. CGM Block Diagram MC68HC908JW32 Data Sheet, Rev Timebase Module (TBM) To SIM ÷ CGMOUT CLOCK SELECT 1 To SIM B S* CIRCUIT SIMDIV2 *WHEN CGMOUT = B From SIM ÷ 3 CGMVCLK To USB CGMINT To SIM Freescale Semiconductor ...
Page 59
... TBM. 5.3.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. Freescale Semiconductor Bit PLLF ...
Page 60
... L, and a power-of-two factor VCLK Modes. The value of the external capacitor and the MC68HC908JW32 Data Sheet, Rev Modulating the voltage on the is equal to the nominal VRS RCLK , is fed back through a programmable P /(N × VDV VCLK Freescale Semiconductor (See ...
Page 61
... The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below f . BUSMAX Freescale Semiconductor 5.5.2 PLL Bandwidth Control 5.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes ...
Page 62
... MC68HC908JW32 Data Sheet, Rev. 6 (See 5.8 ACQ ; and then VCLKDES /R. For stability and lock time reduction, RCLK ) to a value determined RCLK Chapter 19 Electrical to an integer divisor of f RCLK ⎛ ⎞ ⎫ f VCLKDES ⎜ ⎟ ⎬ ------------------------- - ⎝ f ⎠ ⎭ RCLK Freescale Semiconductor , is , BUSDES ...
Page 63
... For proper operation, 8. Verify the choice and L by comparing f operation, f must be within the application’s tolerance of f VCLK as possible to f VCLK. Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. Freescale Semiconductor × ⎛ VCLKDES ⎜ round ------------------------------------ - P ⎝ ...
Page 64
... PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock. 64 NOTE Table 5-1. Numeric Examples f f BUS RCLK 8 MHz 4 MHz 8 MHz 4 MHz 5.3.6 Programming the PLL Circuit. MC68HC908JW32 Data Sheet, Rev does not account for three possible Freescale Semiconductor ...
Page 65
... OSC_XCLKEN (FROM CONFIG) MCU OSC1 RB (4-MHZ Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability. Freescale Semiconductor for routing information, filter network and its effects on PLL CGMXCLK OSC2 CGMXFC 2kΩ RS 2n2 F C2 Figure 5-3. CGM External Connections MC68HC908JW32 Data Sheet, Rev ...
Page 66
... CGMOUT percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by three. 5.4.8 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. 66 5-3.) NOTE MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 67
... VCO clock is driving the base clock, CGMOUT (BCS = 1). (See Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up PLL PLL off Freescale Semiconductor 5.5.1 PLL Control 5.5.2 PLL Bandwidth Control 5.5.4 PLL VCO Range Select 5.5.5 PLL Reference Divider Select ...
Page 68
... Base Clock Selector NOTE Circuit.) PLL.) PRE1 and PRE0 cannot be written when the 5.3.6 Programming the PLL, and VRS MC68HC908JW32 Data Sheet, Rev. 6 Circuit.) Reset Prescaler Multiplier 5.5.4 PLL VCO Range Select . VPR1:VPR0 cannot be written when VCO Power-of-Two Range Multiplier Freescale Semiconductor ...
Page 69
... When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode Freescale Semiconductor LOCK 0 ...
Page 70
... PLL, and . VRS[7:0] cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select MC68HC908JW32 Data Sheet, Rev Bit 0 MUL10 MUL9 MUL8 Bit 0 MUL2 MUL1 MUL0 Bit 0 VRS2 VRS1 VRS0 5.5.1 PLL Control Register.), controls the Freescale Semiconductor ...
Page 71
... When the PLL enters lock, the divided VCO clock, CGMVCLK, divided by three can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the Freescale Semiconductor Exceptions.). Reset initializes the register to NOTE ...
Page 72
... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. 72 NOTE 6.7.3 SIM Break Flag Control MC68HC908JW32 Data Sheet, Rev. 6 Register.) Freescale Semiconductor ...
Page 73
... External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. Freescale Semiconductor 5.3.3 PLL Circuits, Register ...
Page 74
... Time, the external filter network is critical to the is recommended when using a 4MHz reference clock CGMXFC 2 kΩ 100 (a) Figure 5-10. PLL Filter MC68HC908JW32 Data Sheet, Rev. 6 Figure 5-10 (b) is used in CGMXFC 0.22 µ (b) Freescale Semiconductor ...
Page 75
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Figure 6-1. Table 6-1. Signal Name Conventions Description MC68HC908JW32 Data Sheet, Rev. 6 Figure 6 summary of the SIM 75 ...
Page 76
... COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILAD USB LVI Reserved Freescale Semiconductor Bit ...
Page 77
... OSCILLATOR (OSC) MODULE OSC1 STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 CGMRCLK PHASE-LOCKED LOOP (PLL) 6.2.1 Bus Timing In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by six. Freescale Semiconductor IF6 IF5 IF4 ...
Page 78
... Reset Recovery Type POR/LVI All others 78 6.6.2 Stop 6.4 SIM Counter), but an external reset does not. Each of Table 6-2. Reset Recovery Actual Number of Cycles 4163 (4096 + ( MC68HC908JW32 Data Sheet, Rev. 6 Mode.) 6.7 SIM Registers.) Table 6-2 for details. Figure 6-4 Freescale Semiconductor ...
Page 79
... The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. Freescale Semiconductor Figure 6-4. External Reset Timing NOTE ...
Page 80
... The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset CYCLES CYCLES Figure 6-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908JW32 Data Sheet, Rev. 6 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
Page 81
... SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask Freescale Semiconductor (CONFIG).) NOTE MC68HC908JW32 Data Sheet, Rev ...
Page 82
... SP – – 1 CCR – 1[15:8] PC – 1[7:0] Figure 6-9. Interrupt Recovery Timing MC68HC908JW32 Data Sheet, Rev. 6 for details.) The SIM counter is for counter control and Figure 6-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...
Page 83
... When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Freescale Semiconductor Figure 6-10.) FROM RESET ...
Page 84
... The interrupt status registers can be useful for debugging. 84 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908JW32 Data Sheet, Rev. 6 BACKGROUND ROUTINE Table 6-3 summarizes the Freescale Semiconductor ...
Page 85
... Interrupt Status Register 3 Address: $FE06 Bit 7 Read: 0 Write: R Reset Figure 6-14. Interrupt Status Register 3 (INT3) IF15 — Interrupt Flag 15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Freescale Semiconductor IF5 IF4 IF3 IF2 ...
Page 86
... IF6 TIM1 Channel 1 $FFF1 $FFF2 IF5 TIM1 Channel 0 $FFF3 $FFF4 IF4 PLL $FFF5 $FFF6 IF3 IRQ $FFF7 $FFF8 USB Endpoint IF2 $FFF9 $FFFA IF1 USB System $FFFB $FFFC — SWI $FFFD $FFFE — Reset $FFFF MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 87
... SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Freescale Semiconductor Chapter 18 Break Module (BRK).) The SIM puts the CPU into the break MC68HC908JW32 Data Sheet, Rev ...
Page 88
... Figure 6-17. Wait Recovery from Internal Reset 88 WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 6-15. Wait Mode Entry Timing $6E0B $6E0C $00FF $A6 $A6 $01 $ CYCLES CYCLES $6E0B $A6 $A6 MC68HC908JW32 Data Sheet, Rev. 6 SAME SAME SAME $00FE $00FD $00FC $6E RST VCT H RST VCT L Freescale Semiconductor ...
Page 89
... R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. CGMXCLK INT/BREAK IAB STOP +1 Figure 6-19. Stop Mode Recovery from Interrupt Freescale Semiconductor NOTE Figure 6-18 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 6-18. Stop Mode Entry Timing ...
Page 90
... Last reset caused by POR circuit 0 = Read of SRSR 90 (SBSR) — $FE00 (SRSR) — $FE01 (SBFCR) — $FE03 Reserved at this time, then the PIN bit may be set, in addition to whatever PIN COP ILOP ILAD Unimplemented MC68HC908JW32 Data Sheet, Rev Bit 0 SBSW R R Note Bit 0 USB LVI Freescale Semiconductor ...
Page 91
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
Page 92
... System Integration Module (SIM) 92 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 93
... IRQ is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for unauthorized users. Freescale Semiconductor ( applied to IRQ TST MC68HC908JW32 Data Sheet, Rev. 6 ...
Page 94
... NOTE) Figure 7-1. Monitor Mode Circuit MC68HC908JW32 Data Sheet, Rev. 6 0.1 µ 0.1 µF 0.1 µF 100 2.2 nF 4.9152MHz/9.8304MHz (50% DUTY) 8 10k 10k SW1 Freescale Semiconductor RST HC908JW32 DDPLL V SSPLL V SS CGMXFC OSC1 IRQ PTA0 PTA1 PTC1 PTA2 ...
Page 95
... RST after the initial reset to get into monitor mode (when V TST then the COP will be disabled. In the latter situation, after V removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. Freescale Semiconductor External Bus PTA0 ...
Page 96
... Figure 7-3. Break Transaction MC68HC908JW32 Data Sheet, Rev pulling RST low and then high. The 7.4 Security). 7.4 Security.) After the Break SWI SWI Vector Vector Vector Low High Low $FFFD $FFFC $FFFD $FEFD $FEFC $FEFD NEXT START STOP BIT BIT 7 BIT Freescale Semiconductor ...
Page 97
... READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. Wait one bit time after each echo before sending the next byte. Freescale Semiconductor on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0. DD Table 7-3 ...
Page 98
... Figure 7-4. Read Transaction ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 7-5. Write Transaction Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW MC68HC908JW32 Data Sheet, Rev. 6 DATA RETURN DATA DATA Table 7-4 through Table 7-9. DATA RETURN Freescale Semiconductor ...
Page 99
... Table 7-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand None Data Returns contents of next two addresses Returned Opcode $1A ECHO Freescale Semiconductor Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence FROM ...
Page 100
... Reads stack pointer Operand None Data Returns incremented stack pointer value ( Returned high-byte:low-byte order Opcode $0C ECHO 100 Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Command Sequence FROM HOST SP READSP READSP HIGH MC68HC908JW32 Data Sheet, Rev LOW RETURN Freescale Semiconductor ...
Page 101
... Locations $FFF6–$FFFD contain user-defined data. Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. Freescale Semiconductor Command Sequence FROM HOST ...
Page 102
... To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is set is, then the correct security code has been entered and ROM can be accessed. 102 Figure 7-7.) 4096 + 32 CGMXCLK CYCLES 256 BUS CYCLES (MINIMUM NOTE MC68HC908JW32 Data Sheet, Rev Freescale Semiconductor ...
Page 103
... FILE_PTR ADDRESS AS POINTER Figure 7-8. Data Block Format for ROM-Resident Routines During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. Freescale Semiconductor Routine Description ...
Page 104
... FILE_PTR, pointing to the first byte of the data block. 104 Table 7-11. PRGRNGE Routine PRGRNGE Program a range of locations $FE10 16 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 105
... Therefore, care must be taken when calling this routine to prevent an accidental mass erase. The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not used. Freescale Semiconductor ; Indicates 4x bus frequency ; Data size to be programmed ; FLASH start address ...
Page 106
... LDHX #FILE_PTR JSR LDRNGE : 106 7.5.1 PRGRNGE). Table 7-13. LDRNGE Routine LDRNGE Loads data from a range of locations $FA31 10 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N MC68HC908JW32 Data Sheet, Rev. 6 7.5.1 PRGRNGE). Freescale Semiconductor ...
Page 107
... The generic pin names appear in the text that follows. TIM Generic Pin Names: Full TIM Pin Names: References to timer 1 may be made in the following text by omitting the timer number. For example, TCH01 may refer generically to T1CH01. Freescale Semiconductor Table 8-1. Pin Name Conventions T1CH0 T1CH1 PTC0/T1CH0 PTC2/T1CH1 NOTE MC68HC908JW32 Data Sheet, Rev ...
Page 108
... ELS0A CH0F MS0A MS0B ELS0B ELS0A CH1F MS0A Figure 8-1. TIM Block Diagram NOTE MC68HC908JW32 Data Sheet, Rev. 6 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T1CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T1CH1 LOGIC INTERRUPT CH01IE LOGIC CH1IE Freescale Semiconductor ...
Page 109
... With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. Freescale Semiconductor Bit ...
Page 110
... User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 110 NOTE MC68HC908JW32 Data Sheet, Rev. 6 8.4.3 Freescale Semiconductor ...
Page 111
... PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Freescale Semiconductor 8.9.1 TIM Status and Control OVERFLOW ...
Page 112
... Reset the TIM counter and prescaler by setting the TIM reset bit, TRST the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 112 NOTE NOTE MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 113
... Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. Freescale Semiconductor Table 8-3.) NOTE Registers ...
Page 114
... References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. 114 6.7.3 SIM Break Flag Control Register.) Register.) The minimum T2CLK pulse width, 1 ------------------------------------ - + t SU bus frequency NOTE MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 115
... TIM counter active Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. Freescale Semiconductor ...
Page 116
... TIM Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ NOTE Unimplemented MC68HC908JW32 Data Sheet, Rev. 6 TCLK1 2 1 Bit Bit Freescale Semiconductor ...
Page 117
... Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Freescale Semiconductor ...
Page 118
... When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 8- Unbuffered output compare/PWM operation 0 = Input capture operation 118 CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B Unimplemented MC68HC908JW32 Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...
Page 119
... TIM counter overflows. When channel input capture channel, TOVx has no effect. Reset clears the TOVx bit Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow Freescale Semiconductor NOTE Table 8-3 shows how ELSxB and ELSxA work. Reset clears ...
Page 120
... Figure 8-11 shows, the CHxMAX bit takes effect in the cycle OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 8-11. CHxMAX Latency Indeterminate after reset Indeterminate after reset MC68HC908JW32 Data Sheet, Rev. 6 OVERFLOW OVERFLOW OUTPUT COMPARE 2 1 Bit Bit Bit Bit 0 Freescale Semiconductor ...
Page 121
... Address: $0014 Bit 7 Read: Bit 15 Write: Reset: Figure 8-14. TIM Channel 1 Register High (TCH1H) Address: $0015 Bit 7 Read: Bit 7 Write: Reset: Figure 8-15. TIM Channel 1 Register Low (TCH1L) Freescale Semiconductor Indeterminate after reset Indeterminate after reset MC68HC908JW32 Data Sheet, Rev. 6 I/O Registers ...
Page 122
... Timer Interface Module (TIM) 122 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 123
... If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 Figure ...
Page 124
... Figure 9-1. Timebase Block Diagram TBR2 TBR1 TBR0 TACK Unimplemented R MC68HC908JW32 Data Sheet, Rev. 6 ÷ 2 ÷ 2 ÷ 8192 ÷ 16384 ÷ 32768 TBMINT 000 001 TBIF 010 R 011 SEL 100 101 110 111 2 1 Bit 0 TBIE TBON Reserved Freescale Semiconductor TBON TBIE ...
Page 125
... TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. The interrupt vector is defined in Table 6-3. Interrupt Sources. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. Freescale Semiconductor Timebase Interrupt Rate TBR0 Divider Hz 0 262144 ~0 ...
Page 126
... If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during STOP mode. In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction. 126 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 127
... The full names of the SPI I/O pins are shown in follows. SPI Generic Pin Names: Full SPI SPI Pin Names: Figure 10-1 summarizes the SPI I/O registers. Freescale Semiconductor Table 10-1. The generic pin names appear in the text that Table 10-1. Pin Name Conventions MISO MOSI SS PTE6/MISO PTE5/MOSI PTE7/SS MC68HC908JW32 Data Sheet, Rev ...
Page 128
... Unimplemented Figure 10-1. SPI I/O Register Summary NOTE 10.13.1 SPI Control Figure 10-3.) Register.) Through the SPSCK pin, the baud rate generator of the MC68HC908JW32 Data Sheet, Rev CPOL CPHA SPWOM SPE SPTE MODFEN SPR1 Reserved R Register.) Freescale Semiconductor Bit 0 SPTIE 0 SPR0 ...
Page 129
... DIVIDER ÷ 32 ÷ 128 SPMSTR SPE SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST MASTER MCU SHIFT REGISTER BAUD RATE GENERATOR Figure 10-3. Full-Duplex Master-Slave Connections Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER CLOCK SELECT ...
Page 130
... Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE). 130 10.5 Transmission NOTE NOTE MC68HC908JW32 Data Sheet, Rev. 6 10.7.2 Mode Fault Error.) Formats.) Freescale Semiconductor ...
Page 131
... Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. Freescale Semiconductor 10.7.2 Mode Fault 1 ...
Page 132
... MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. 132 MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 Figure 10-7.) The internal SPI clock in the master is a free-running MC68HC908JW32 Data Sheet, Rev BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB Figure 10-7. This delay is Freescale Semiconductor ...
Page 133
... The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high. the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0). Freescale Semiconductor INITIATION DELAY MSB 1 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN SPSCK = INTERNAL CLOCK ÷ ...
Page 134
... SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. MC68HC908JW32 Data Sheet, Rev BIT BIT BIT LSB MSB BIT BIT BIT BYTE Freescale Semiconductor ...
Page 135
... OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. Freescale Semiconductor Figure 10-4 and Figure ...
Page 136
... CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure Freescale Semiconductor 10-11.) ...
Page 137
... Four SPI status flags can be enabled to generate CPU interrupt requests. Flag SPTE Transmitter empty SPRF Receiver full OVRF Overflow MODF Mode fault Freescale Semiconductor NOTE 10.5 Transmission NOTE NOTE Table 10-2. SPI Interrupts Request SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request ...
Page 138
... If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request. 138 Figure 10-11.) SPTE SPTIE SPE SPRIE SPRF MC68HC908JW32 Data Sheet, Rev. 6 NOT AVAILABLE SPI TRANSMITTER CPU INTERRUPT REQUEST NOT AVAILABLE SPI RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor ...
Page 139
... To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit status bit is cleared during the break state, it remains cleared when the MCU exits the break state. Freescale Semiconductor 10.8 Chapter 6 System Integration Module MC68HC908JW32 Data Sheet, Rev ...
Page 140
... MCUs exchange a byte of data in eight serial clock cycles. 140 ) capability (requiring software support master peripherals, MOSI becomes an open-drain output 2 C communication, the MOSI and MISO pins 2 C peripheral and through a pullup resistor to V MC68HC908JW32 Data Sheet, Rev Freescale Semiconductor ...
Page 141
... The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. (See SPE SPMSTR ( Note Don’t care Freescale Semiconductor Figure 10-12. BYTE 1 BYTE 2 Figure 10-12. CPHA/SS Timing NOTE 10.7.2 Mode Fault Table 10-3.) Table 10-3. SPI Configuration MODFEN SPI Configuration X ...
Page 142
... To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 142 Table 10- SPMSTR CPOL CPHA Reserved 10-12.) Reset sets the CPHA bit. MC68HC908JW32 Data Sheet, Rev Bit 0 SPWOM SPE SPTIE Freescale Semiconductor ...
Page 143
... During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit Receive data register full 0 = Receive data register not full Freescale Semiconductor ...
Page 144
... For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See Fault Error.) 144 NOTE Select).) MC68HC908JW32 Data Sheet, Rev. 6 10.7.2 Mode Freescale Semiconductor ...
Page 145
... Address: $004E Bit 7 Read: R7 Write: T7 Reset: R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. Freescale Semiconductor Baud Rate Divisor (BD) CGMOUT = ------------------------- - × Figure ...
Page 146
... Serial Peripheral Interface Module (SPI) 146 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 147
... NRZI (Non-Return-to Zero Inserted) encoding/decoding – Bit-stuffing – Sync detection – End-of-packet detection • USB reset options: – Internal MCU reset generation – CPU interrupt request generation • Suspend and resume operations, with remote wakeup support Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 147 ...
Page 148
... Full speed devices are terminated with the pull-up resistor on the D+ line. 148 USB Control Logic USB Endpoint Controller System Bus Figure 11-1. The module involves six major blocks - USB MC68HC908JW32 Data Sheet, Rev. 6 USB Request Processor Freescale Semiconductor ...
Page 149
... The endpoint type and direction of all endpoint software programmable to either BULK or INTERRUPT and either IN or OUT respectively. The endpoint configuration is summarized in Table 11-1 Endpoint Number Freescale Semiconductor Table 11-1. Endpoint Summary Configuration Interface Number Number — — 1 EP1INT 1 EP2INT ...
Page 150
... ACK is returned to the host. No user notification is provided. Passed to the user as a vendor specific request. NOTE: SETUP flag, TFRC_OUT flag and DVALID_OUT flag will be set. User should decode the request via reading the endpoint 0 data registers (UE0D0-UE0D7). MC68HC908JW32 Data Sheet, Rev. 6 Handling Freescale Semiconductor ...
Page 151
... Endpoint Controller The module has four independent endpoint controllers that managed the data transfer between CPU and the USB host. Each of these endpoint can be configured to either one of the two modes - bulk or interrupt. Freescale Semiconductor NOTE NOTE MC68HC908JW32 Data Sheet, Rev. 6 ...
Page 152
... USB Endpoint Interrupt TFRC3 USB Endpoint Interrupt TFRC4 USB Endpoint Interrupt SETUP USB System Interrupt SOF USB System Interrupt CONFIG_CHG USB System Interrupt USBRST USB System Interrupt RESUMEF USB System Interrupt SUSPND USB System Interrupt MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 153
... Reset: Read: USB EP2 Data Size $005A Register Write: (UEP2DSR) Reset: Read: USB EP3 Data Size $005B Register Write: (UEP3DSR) Reset: Read: USB EP4 Data Size $005C Register Write: (UEP4DSR) Reset: Freescale Semiconductor USBCLKEN TFC4IE TFC3IE SETUP SOF SETUPIE SOFIE EP0_STALL ...
Page 154
... UE0D30_ OUT OUT OUT OUT UE0D43_ UE0D42_ UE0D41_ UE0D40_ OUT OUT OUT OUT UE0D53_ UE0D52_ UE0D51_ UE0D50_ OUT OUT OUT UE0D63_ UE0D62_ UE0D61_ UE0D60_ OUT OUT OUT OUT UE0D73_ UE0D72_ UE0D71_ UE0D70_ OUT OUT OUT OUT = Reserved R Freescale Semiconductor OUT OUT ...
Page 155
... SET_FEATURE command. The USB control logic ensures the forced resume duration is greater than 3ms. Reading this bit always returns zero. Writing zero to the bit has no effect Generates forced RESUME condition on the USB data lines 0 = Default value Freescale Semiconductor ...
Page 156
... Writing one to the bit has no effect. Reset clears this bit USB bus activity is detected while the device is in SUSPEND mode USB bus activity is detected 156 CONFIG_ SETUP SOF CHG Figure 11-4. USB Status Register MC68HC908JW32 Data Sheet, Rev Bit 0 USBRST RESUMEF SUSPND Freescale Semiconductor ...
Page 157
... This read/write bit enables a CPU interrupt request when a configuration change from zero to one is detected or CONFIG_CHG flag of USB status register (USBSR) is set. Reset clears this bit CPU interrupt is enabled when CONFIG_CHG flag in USBSR is set 0 = CPU interrupt is disabled when CONFIG_CHG flag in USBSR is set Freescale Semiconductor ...
Page 158
... This read/write bit indicates the data in the EP0 buffer is completely transferred to the host. When the bit is set, all successive IN packet is responded by NAK. Writing zero to clear this bit. Writing one to the bit has no effect Endpoint data transfer completed 0 = Default status 158 DVALID_IN DSIZE1_IN DSIZE0_IN MC68HC908JW32 Data Sheet, Rev Bit 0 TFRC_IN DVALID_OUT TFRC_OUT Freescale Semiconductor ...
Page 159
... CPU attention is required. User must clear this bit in order to receive the next OUT packet, otherwise all successive OUT packet is responded NAK by the module. Reset clears this bit Data in the endpoint buffer is valid 0 = Data in the endpoint buffer is not valid Freescale Semiconductor ...
Page 160
... This bit selects the type of the endpoint. When USBEN is set, this bit has no effect. Table 11-5. Mode selection for Endpoint type 160 Table 11-4. Buffer Size Selection Table SIZE[1:0] Buffer Size 00 8 Bytes 01 16 Bytes 10 32 Bytes 11 64 Bytes NOTE MODE[1:0] Endpoint Type 00 Endpoint Disable 01 — 10 Bulk 11 Interrupt MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 161
... This register indicates the base address pointer for the endpoint buffer area. The pointer location must align to the 8 bytes boundary. BASEx[2:0] specifies only the 3 address bits A5-A3. When USBEN is set, these bit have no effect. Table 11-6. BASEx[2:0] Address Definition %0001 0000 A15–A8 Freescale Semiconductor DSIZE6 ...
Page 162
... The IN buffer can be accessed by writing to the registers. 162 EP4INT EP3INT UE0Dx6_ UE0Dx5_ UE0Dx4_ UE0Dx3_ OUT OUT OUT OUT UE0Dx6_ UE0Dx5_ UE0Dx4_ UE0Dx3_ Unaffected by reset MC68HC908JW32 Data Sheet, Rev Bit 0 EP2INT EP1INT UE0Dx2_ UE0Dx1_ UE0D0x_ OUT OUT OUT UE0Dx2_ UE0Dx1_ UE0Dx0_ Freescale Semiconductor ...
Page 163
... CPU interrupt at the different clock phase. The CPU interrupt can be masked by clearing the PS2IEN bit. The waveform diagram is shown in When the module is enabled, the output port status is continuous monitored and stored in PSTATUS flag. PTE2/PS2CLK/D+ Figure 12-1. PS2 Clock Generator Block Diagram Freescale Semiconductor Figure PSTATUS PS2IEN CLKEN ...
Page 164
... This flag is set when PS2 interrupt is trigger by the interrupt generator. Writing one to this bit clears the flag. Reset clears this flag CPU interrupt is pending 0 = CPU interrupt is not pending 164 CLKEN = 0 CPU Interrupt Trigger PS2IF PRE CSEL1 CSEL0 Unimplemented R MC68HC908JW32 Data Sheet, Rev Bit 0 PS2IEN CLKEN PS2EN Reserved Freescale Semiconductor ...
Page 165
... Open drain clock output is disabled PS2EN — PS2 Clock Generator Module Enable This read/write bit enables the module clock source. Reset clears this bit Module enabled 0 = Module disabled Freescale Semiconductor PS2 Clock Generator Control and Status Registers Table 12-1. CSEL[1:0] Divider Ratio CSEL[1:0] Divider Ratio ...
Page 166
... PS2 Clock Generator (PS2CLK) 166 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 167
... Port D Data Register $0003 Write: (PTD) Reset: Read: Port E Data Register $0008 Write: (PTE) Reset: Read: Data Direction Register A $0004 Write: (DDRA) Reset: Figure 13-1. I/O Port Register Summary Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 ...
Page 168
... DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 DDRE3 DDRE2 LEDB3 LEDB2 LEDB1 LEDB0 PTD2PD DPPULLEN PTE3P PTE2P PULL3EN PULL2EN PULL1EN PULL0EN Pin Control Bit KBIE0 PTA0/KBA0 KBIE1 PTA1/KBA1 KBIE2 PTA2/KBA2 KBIE3 PTA3/KBA3 KBIE4 PTA4/KBA4 KBIE5 PTA5/KBA5 KBIE6 PTA6/KBA6 KBIE7 PTA7/KBA7 Freescale Semiconductor ...
Page 169
... DDRC0 1 DDRC1 C 2 DDRC2 3 DDRC3 0 DDRD0 1 DDRD1 2 DDRD2 3 DDRD3 D 4 DDRD4 5 DDRD5 6 DDRD6 7 DDRD7 Freescale Semiconductor Module Control Module Register LED POCR1 ($1A) PULLUP PULLCR ($3E) LED POCR1 ($1A) PULLUP PULLCR ($3E) LED POCR1 ($1A) PULLUP PULLCR ($3E) LED POCR1 ($1A) PULLUP PULLCR ($3E) LED POCR1 ($1A) PULLUP PULLCR ($3E) LED ...
Page 170
... Figure 13-2. Port A Data Register (PTA) (KBI).) MC68HC908JW32 Data Sheet, Rev. 6 Pin Control Bit USBEN PTE2P PTE2/D+ PS2EN USBEN PTE3P PTE3/D– PTE3IE PTE4/SPSCK PTE5/MOSI SPE PTE6/MISO PTE7/ Bit 0 PTA2 PTA1 PTA0 KBA2 KBA1 KBA0 Optional Optional Optional pullup pullup pullup Freescale Semiconductor ...
Page 171
... When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor 6 5 ...
Page 172
... Figure 13-5. Port B Data Register (PTB) Options.) Options.) MC68HC908JW32 Data Sheet, Rev. 6 Accesses to PTA Read Write (3) Pin PTA[7:0] PTA[7:0] PTA[7: Bit 0 PTB2 PTB1 PTB0 LED drive LED drive LED drive Optional Optional Optional pullup pullup pullup Freescale Semiconductor ...
Page 173
... The data latch can always be written, regardless of the state of its data direction bit. DDRB PTB Bit Bit don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor DDRB6 DDRB5 DDRB4 DDRB3 ...
Page 174
... PTC3 Unaffected by reset = Unimplemented Figure 13-8. Port C Data Register (PTC) Table 13-4. Port C Priority Table MSxB:MSxA Feature 01/10/11 Timer function pins 00 Port logic control (TIM)) NOTE MC68HC908JW32 Data Sheet, Rev Bit 0 PTC2 PTC1 PTC0 T1CH1 T1CLK T1CH0 (TIM)) Freescale Semiconductor ...
Page 175
... The data latch can always be written, regardless of the state of its data direction bit. DDRC PTC Bit Bit ( don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor DDRC3 Unimplemented NOTE DDRCx ...
Page 176
... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 176 PTD6 PTD5 PTD4 PTD3 Unaffected by reset Optional Pullup = Unimplemented DDRD6 DDRD5 DDRD4 DDRD3 NOTE MC68HC908JW32 Data Sheet, Rev Bit 0 PTD2 PTD1 PTD0 Optional Pullup 2 1 Bit 0 DDRD2 DDRD1 DDRD0 Freescale Semiconductor ...
Page 177
... PTD Bit Bit don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor DDRDx RESET PTDx Figure 13-13. Port D I/O Circuit Table 13-6 summarizes the operation of the port D pins. Table 13-6. Port D Pin Functions Accesses ...
Page 178
... PTE5 PTE4 PTE3 Unaffected by reset D– high current open drain Optional 5kΩ pullup to VDD External Interrupt MISO MOSI SPSCK = Unimplemented MC68HC908JW32 Data Sheet, Rev Bit 0 PTE2 D+ high current open drain Optional USB pullup to VREF33 Optional 5kΩ pullup to VDD PS2CLK Freescale Semiconductor ...
Page 179
... The PTE2 USB pullup enable bits, DPPULLEN, in the port option control register 2 (POCR2) enable USB pullups to VREF33 on PTE2 for USB operation. Either of PTE2P or DPPULLEN bit can be activated at the one time, DPPULLEN bit has higher priority, it will always override the setting of PTE2P bit. Freescale Semiconductor Table 13-7. PTE2/D+ Priority Table Data USB D+ ...
Page 180
... E bits from 180 NOTE Table 13-5 . Port C Pin DDRE6 DDRE5 DDRE4 DDRE3 Unimplemented NOTE MC68HC908JW32 Data Sheet, Rev. 6 14.7 IRQ Status and Control Chapter 12 PS2 Clock Generator Chapter 11 USB 2.0 FS Functions.) Chapter 10 Serial Peripheral Interface 2 1 Bit 0 DDRE2 Freescale Semiconductor ...
Page 181
... Bit Bit don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor DDREx RESET PTEx Figure 13-16. Port E I/O Circuit Table 13-5 summarizes the operation of the port E pins. Table 13-9. Port E Pin Functions Accesses ...
Page 182
... This read/write bit disables the pullup option for pin PTD2. The pullup resistor is default enabled after reset Pullup option disabled 0 = Pullup option enabled 182 LEDB6 LEDB5 LEDB4 LEDB3 PTD7PD PTD3PD PTD2PD DPPULLEN MC68HC908JW32 Data Sheet, Rev Bit 0 LEDB2 LEDB1 LEDB0 Bit 0 PTE3P PTE2P Freescale Semiconductor ...
Page 183
... Reset: 0 Figure 13-17. Pullup Control Register (PULLCR) PULL[7:0]EN — Pullup Enable Bit These read/write bits enables the embedded pullup resistor associated with the corresponding port pin. Reset clears this bit Pullup resistor is enabled 0 = Pullup resistor is disabled Freescale Semiconductor NOTE PULL6EN PULL5EN ...
Page 184
... Input/Output (I/O) Ports 184 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 185
... The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Freescale Semiconductor MC68HC908JW32 Data Sheet, Rev. 6 Figure 14-1 ...
Page 186
... NOTE "1" CLR IRQ FF MODE "1" READ IOCR CLR Figure 14-1. IRQ Module Block Diagram MC68HC908JW32 Data Sheet, Rev. 6 6.5 Exception HIGH VOLTAGE DETECT IRQF SYNCHRO- NIZER IMASK PTE3IF Freescale Semiconductor TO MODE SELECT LOGIC TO CPU FOR BIL/BIH INSTRUCTIONS IRQ INTERRUPT REQUEST ...
Page 187
... Use the BIH or BIL instruction to read the logic level on the IRQ pin. When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to V disabled by setting the IRQPD bit in the IRQ option control register ($001C). Freescale Semiconductor Bit Read: 0 ...
Page 188
... This read-only status bit is high when the IRQ interrupt is pending IRQ interrupt pending 0 = IRQ interrupt not pending 188 Figure (SIM).) IRQF Unimplemented MC68HC908JW32 Data Sheet, Rev. 6 14-1. Therefore, the IRQ status and control 2 1 Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 189
... PTE3 pin for interrupt function to the IRQ interrupt. Setting PTE3IE also enables the internal pullup on PTE3 pin PTE3 interrupt enabled; triggers IRQ interrupt 0 = PTE3 interrupt disabled IRQPD — IRQ Pullup Disable This read/write bit controls the pullup option for the IRQ pin Internal pullup is disconnected 0 = Internal pull-up is connected between IRQ pin and V Freescale Semiconductor ...
Page 190
... External Interrupt (IRQ) 190 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 191
... Pin Name Conventions The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 15-1. The generic pin name appear in the text that follows. KBI Generic Pin Name KBA0–KBA7 Freescale Semiconductor Bit ...
Page 192
... Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. 192 ACKK V REG RESET CLR KEYBOARD INTERRUPT FF MODEK NOTE MC68HC908JW32 Data Sheet, Rev. 6 INTERNAL BUS VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request IMASKK Freescale Semiconductor ...
Page 193
... Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. Freescale Semiconductor NOTE MC68HC908JW32 Data Sheet, Rev. 6 Functional Description ...
Page 194
... This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 194 KEYF Unimplemented MC68HC908JW32 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...
Page 195
... If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See Freescale Semiconductor ...
Page 196
... Keyboard Interrupt Module (KBI) 196 MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 197
... RESET VECTOR FETCH COPCTL WRITE COPEN (FROM SIM) COPD (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG) Freescale Semiconductor SIM 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 16-1. COP Block Diagram MC68HC908JW32 Data Sheet, Rev ...
Page 198
... The power-on reset (POR) circuit in the SIM clears the COP prescaler 4096 CGMRCLK cycles after power-up. 16.3.5 Internal Reset An internal reset clears the SIM counter and the COP counter. 198 NOTE NOTE Figure 16-1. 16.4 COP Control MC68HC908JW32 Data Sheet, Rev During the break state, TST Register) clears the COP Freescale Semiconductor ...
Page 199
... COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 Read: Write: Reset: Figure 16-3. COP Control Register (COPCTL) 16.5 Interrupts The COP does not generate CPU interrupt requests. Freescale Semiconductor LVIRSTD LVIPWRD ...
Page 200
... COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 16.8 COP Module During Break Mode The COP is disabled during a break interrupt when V 200 is present on the IRQ pin or on the RST pin. TST is present on the RST pin. TST MC68HC908JW32 Data Sheet, Rev. 6 Freescale Semiconductor ...