MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet
MCHC908MR8CFAE
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MC68HC908MR8 Technical Data M68HC08 Microcontrollers Rev. 4.1 MC68HC908MR8/D August 16, 2005 freescale.com ...
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... Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc Equal Opportunity/Affirmative Action Employer. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor © Freescale, Inc., 2005 Technical Data 3 ...
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... Technical Data 4 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... Section 14. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 279 Section 15. Computer Operating Properly (COP 291 Section 16. External Interrupt (IRQ 297 Section 17. Low-Voltage Inhibit (LVI 305 Section 18. Analog-to-Digital Converter (ADC 311 Section 19. Power-On Reset (POR 327 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor (PWMMC 139 List of Paragraphs List of Paragraphs Technical Data 5 ...
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... List of Paragraphs Section 20. Break (BRK 329 Section 21. Electrical Specifications 339 Section 22. Mechanical Specifications . . . . . . . . . . . . . 351 Section 23. Ordering Information . . . . . . . . . . . . . . . . . 355 Technical Data — Revision History . . . . . . . . . . . . . . . . 357 Technical Data 6 List of Paragraphs MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ ...
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... FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 63 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Section 5. Configuration Register (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CONFIG Bits Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Section 7. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction ...
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... CGM Base Clock Output (CGMOUT 124 CGM CPU Interrupt (CGMINT 124 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 129 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 131 Interrupts .132 Wait Mode 133 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . . 124 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor CGM During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 134 Acquisition/Lock Time Definitions .134 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 136 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 137 Section 9. Pulse-Width Modulator for Motor Control (PWMMC) Contents ...
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... Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Security 196 Section 11. Timer Interface A (TIMA) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 TIMA Counter Prescaler .204 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Output Compare 205 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 206 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .206 Pulse-Width Modulation (PWM 207 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 208 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 209 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Interrupts ...
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... Inversion of Transmitted Output 255 Transmitter Interrupts .255 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Receiver Wakeup 260 Receiver Interrupts 261 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Wait Mode 262 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor SCI During Break Module Interrupts .262 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PTE2/TxD (Transmit Data 263 PTB0/RxD (Receive Data 263 I/O Registers 263 SCI Control Register 264 SCI Control Register 267 SCI Control Register 3 ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .307 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 LVI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 308 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 Wait Mode 309 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Section 18. Analog-to-Digital Converter (ADC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Continuous Conversion ...
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... Section 21. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Functional Operating Range 341 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 343 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 346 Table of Contents . . . . . . . . . . . . 348 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 22. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 32-Pin LQFP (Case #873A 352 28-Pin PDIP (Case #710 353 28-Pin SOIC (Case #751F .353 Section 23. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 Introduction ...
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... Table of Contents Technical Data 20 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Title MCU Block Diagram QFP and DIP/SOIC Pin Assignments . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Control, Status, and Data Registers FLASH Control Register (FLCR FLASH Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Block Protect Register (FLBPR FLASH Block Protect Address ...
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... Dead-Time and Small Pulse Widths 157 PWM Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 PWM Output Control Register (PWMOUT 159 Dead-Time Insertion During OUTCTL = 160 Dead-Time Insertion During OUTCTL = 161 PWM Disabling Scheme .162 PWM Disable Mapping Write-Once Register (DISMAP 163 List of Figures MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor PWM Disabling Decode Scheme . . . . . . . . . . . . . . . . . . . .164 PWM Disabling in Automatic Mode . . . . . . . . . . . . . . . . . . 166 PWM Disabling in Manual Mode (Example 167 PWM Disabling in Manual Mode (Example 167 PWM Software Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 PWMEN and PWM Pins .169 PWM Counter Register High (PCNTH) ...
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... I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 280 Port A Data Register (PTA 281 Data Direction Register A (DDRA 282 Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Port B Data Register (PTB 284 Data Direction Register B (DDRB 285 Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 List of Figures MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Port C Data Register (PTC 287 Data Direction Register C (DDRC 288 Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 292 COP Control Register (COPCTL .294 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 298 IRQ I/O Register Summary ...
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... List of Figures Technical Data 26 MC68HC908MR8 — Rev 4.1 List of Figures Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Title Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VCO Frequency Multiplier (N) Selection 131 PWM Prescaler 148 PWM Reload Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 PWM Data Overflow and Underflow Conditions ...
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... SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . 278 Port A Pin Functions 283 Port B Pin Functions 286 Port C Pin Functions 289 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 List of Tables MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 1. General Description Introduction .29 Features .30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Pin Assignments ...
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... Optional computer operating properly (COP) reset – Low-voltage detection with optional reset – Illegal opcode detection with optional reset – Illegal address detection with optional reset – Fault detection with optional PWM disabling General Description MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Available packages: – 32-pin low-profile quad flat pack (LQFP) – 28-pin dual in-line package (PDIP) – 28-pin small outline package (SOIC) Low-power design, fully static with stop and wait modes ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 7680 BYTES USER RAM — 256 BYTES MONITOR ROM — 313 BYTES USER VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...
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... Pin Assignments Figure 1-2 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor shows 32-pin QFP and 28-pin DIP/SOIC pin assignments SSA OSC2 2 OSC1 3 CGMXFC 4 32-PIN QFP IRQ 5 PWM1 6 PWM2 7 PWM3 REFH 27 RST DDA SSA 24 OSC2 5 28-PIN 23 6 OSC1 DIP/SOIC CGMXFC 22 7 IRQ ...
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... The MCU operates 0.1 µ Note: Component values shown represent typical applications. Figure 1-3. Power Supply Bypassing Section 8. Clock Generator Module (SIM). General Description Figure 1-3 MCU (CGM). Section 7. System MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... On the 32-pin QFP package, all seven bits (PTA6/ATD6–PTA0/ATD0) of the port are available. On the 28-pin package, four bits (PTA3/ATD3–PTA0/ATD0) are available. PTA3–PTA0 have high current source and sink capability. See Section 14. Input/Output (I/O) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor (IRQ). and V ) DDA SSA ...
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... See Modulator for Motor Control Technical Data 36 Section 11. Timer Interface A Section 12. Timer Interface B Ports, and Section 13. Serial Communications (SCI). Section 9. Pulse-Width Modulator for and Section 14. Input/Output (I/O) (PWMMC). General Description (TIMB), Section 14. Ports. Section 9. Pulse-Width MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in • • • • MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 2. Memory Map Introduction .37 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . .38 Reserved Memory Locations .38 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 8 Kbytes of FLASH ...
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... I/O register summary, reserved addresses are marked with the word reserved. Some I/O bits are reserved. Writing to a reserved bit can have unpredictable effects on MCU operation. In register figures, reserved bits are marked with the letter R. Technical Data 38 MC68HC908MR8 — Rev 4.1 Memory Map Freescale Semiconductor ...
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... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor $FE00, system integration module (SIM) break status register (SBSR) $FE01, SIM reset status register (SRSR) $FE03, SIM break flag control register (SBFCR) $FE08, FLASH control register (FLCR) $FF57, FLASH test control register (FLTCR) ...
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... Memory Map $0000 ↓ $005F $0060 ↓ $015F $0160 ↓ $DFFF $E000 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 ↓ $FF48 $FF49 ↓ $FF7D MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... See page 282 Unaffected X = Indetermi- nate Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 10) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor FLASH BLOCK PROTECT REGISTER (FLBPR) ↓ UNIMPLEMENTED — 83 BYTES ↓ VECTORS — 45 BYTES (46 including $FFFF) Low byte of reset vector COP Control Register (COPCTL) Figure 2-1 ...
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... CH0IE MS0B MS0A Reserved R Bold Memory Map Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC1 DDRC0 PS2 PS1 PS0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit Bit CH0MA ELS0B ELS0A TOV0 Buff- = Unimplemented ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... PWM Control Register 1 $0020 (PCTL1) See page 175. PWM Control Register 2 $0021 (PCTL2) See page 177 Unaffected X = Indetermi- nate Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 10) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Read: Bit Write: Reset: Read: Bit 7 6 ...
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... Bit 0 FMODE FINT1 FFLAG 0 0 FPIN1 FTACK OUT4 OUT3 OUT2 OUT1 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Buff- = Unimplemented ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... PWM 5 Value Register $0033 Low (PVAL5L) See page 174. PWM 6 Value Register $0034 High (PVAL6H) See page 174 Unaffected X = Indetermi- nate Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 10) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Read: Bit 7 Bit 6 Bit 5 Write: Reset ...
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... Reserved R Bold Memory Map Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 Buff- = Unimplemented ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... TIMB Counter Register Low $0053 (TBCNTL) See page 240. TIMB Counter Modulo Register High (TB- $0054 MODH) See page 241 Unaffected X = Indetermi- nate Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 10) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Read Write Reset ...
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... Bit 3 Bit 2 Bit 1 Bit CH0MA ELS0B ELS0A TOV0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 CH1MA ELS1B ELS1A TOV1 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit VRS7 VRS6 VRS5 VRS4 Buff- = Unimplemented ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... Break Address Register $FE0D Low (BRKL) See page 334. Break Status and Con- $FE0E trol Register (BRKSCR) See page 333 Unaffected X = Indetermi- nate Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 10) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Read Write: Reset: ...
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... Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 10) Technical Data 50 Bit LVI TRPS- OUT BPR7 BPR6 BPR5 BPR4 Unaffected by reset Low byte of reset vector Clear COP counter Unaffected by reset = Reserved R Bold Memory Map Bit BPR3 BPR2 BPR1 BPR0 = Buff- = Unimplemented ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
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... Table 2-1 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor is a list of vector locations. Table 2-1. Vector Addresses Address $FFD2 SCI transmit vector (high) $FFD3 SCI transmit vector (low) $FFD4 SCI receive vector (high) $FFD5 SCI receive vector (low) $FFD6 SCI error vector (high) ...
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... PLL vector (low) $FFFA IRQ vector (high) $FFFB IRQ vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) $FFFF Reset vector (low) Section 10. Monitor ROM (MON). Memory Map Vector MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 53
... Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the central processor unit (CPU) registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Introduction .53 Functional Description .53 Random-Access Memory (RAM) Technical Data ...
Page 54
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 54 Random-Access Memory (RAM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 55
... FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 4. FLASH Memory Introduction .55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .56 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .57 FLASH Page Erase Operation ...
Page 56
... Technical Data 56 $E000–$FDFF, user memory $FF7E, block protect register (FLBPR) $FE08, FLASH control register (FLCR) $FFD2–$FFFF, locations reserved for user-defined interrupt and reset vectors 1 prevents viewing of the FLASH contents. FLASH Memory MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 57
... This read/write bit configures the memory for mass erase operation. ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor $FE08 Bit ...
Page 58
... Program operation selected 0 = Program operation unselected register. address range desired. (minimum of 10 µs). NVS (minimum of 1 ms). Erase (minimum of 5 µs). NVH (typically 1 µs), the memory can be accessed in RCV read mode again. 21.7 Memory Characteristics. FLASH Memory NVH MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 59
... Set the PGM bit in the FLASH control register. This configures the 2. Read the block protect register. 3. Write to any FLASH address with any data within the page MC68HC908MR8 — Rev 4.1 Freescale Semiconductor address range desired. (minimum of 10 µs). NVS (minimum of 4 ms). ...
Page 60
... PROG programmed. (minimum of 5 µs). NVH (typically 1 µs), the memory can be accessed in RCV read mode again. Characteristics. Figure 4-2 for an algorithm for programming a row (32 bytes) of FLASH Memory . PROG maximum. See 21.7 PROG MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 61
... The time between each address change, or the time between the last FLASH address programmed to clear the PGM bit, must not exceed the maximum programming time, t Figure 4-2. FLASH Programming Algorithm MC68HC908MR8 — Rev 4.1 Freescale Semiconductor . PROG FLASH Memory FLASH Memory FLASH Programming Algorithm ...
Page 62
... Technical Data 62 4.3.2 FLASH Block Protect Register. Once the block protect present on the IRQ pin. The presence FLASH Memory on the HI MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 63
... FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory at $FFFF. With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64-byte page boundaries) within the FLASH memory. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor $FF7E Bit BPR7 ...
Page 64
... Technical Data 64 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH 1 1 FLBPR VALUE BLOCK PROTECT Figure 4-4. FLASH Block Protect Address ↓ ↓ ↓ FLASH Memory the IRQ pin will bypass the HI MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 0 ...
Page 65
... FLASH will be in standby mode. NOTE: Standby mode is the power-saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor FLASH Memory FLASH Memory FLASH Programming Algorithm Technical Data 65 ...
Page 66
... FLASH Memory Technical Data 66 FLASH Memory MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 67
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Introduction .67 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 CONFIG Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Resets caused by the low-voltage inhibit (LVI) module Power to the LVI module Computer operating properly (COP) module Top-side pulse-width modulator (PWM) polarity Bottom-side PWM polarity ...
Page 68
... Figure 5-1. CONFIG Register 1 = Edge-aligned mode enabled 0 = Center-aligned mode enabled Section 9. Pulse-Width Modulator for Motor (PWMMC Negative polarity 0 = Positive polarity Configuration Register (CONFIG) , and remains at or below that level Bit 0 LVIP- STOPE COPD Section 9. (PWMMC). MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 0 ...
Page 69
... STOPE enables the STOP instruction. See Processor Unit COPD — COP Disable Bit COPD disables the COP module. See Operating Properly MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 9. Pulse-Width Modulator for Motor (PWMMC Negative polarity 0 = Positive polarity 1 = Six independent PWMs 0 = Three complementary PWM pairs (LVI) ...
Page 70
... Configuration Register (CONFIG) Technical Data 70 Configuration Register (CONFIG) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 71
... The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual, Freescale document number CPU08RM/AD, contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction .71 Features .72 CPU Registers .72 Accumulator ...
Page 72
... Figure 6-1. CPU Registers Central Processor Unit (CPU) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 0 CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 73
... In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. Read: Write: Re- set: The index register can serve also as a temporary data storage location. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Unaffected by reset Figure 6-2. Accumulator (A) Bit 15 ...
Page 74
... RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations. Technical Data 74 Bit Figure 6-4. Stack Pointer (SP) Central Processor Unit (CPU) Bit MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 75
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Re- set: MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit Loaded with vector from $FFFE and $FFFF Figure 6-5 ...
Page 76
... CPU registers are saved on the stack, but before the interrupt vector is fetched. Technical Data 76 Bit Indeterminate Figure 6-6. Condition Code Register (CCR Overflow overflow 1 = Carry between bits 3 and carry between bits 3 and 4 Central Processor Unit (CPU Bit MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 77
... Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result ...
Page 78
... Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock Central Processor Unit (CPU) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 79
... Arithmetic Shift Right ASR opr,X ASR opr,X ASR opr,SP BCC rel Branch if Carry Bit Clear MC68HC908MR8 — Rev 4.1 Freescale Semiconductor provides a summary of the M68HC08 instruction set. Description A ← (A) + (M) + (C) A ← (A) + (M) SP ← (SP) + (16 « M) H:X ← (H:X) + (16 « ← (A) & (M) ...
Page 80
... REL PC ← (PC rel ? ( – – – – – – REL Central Processor Unit (CPU) Effect on CCR DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 IMM DIR EXT IX2 – IX1 SP1 9EE5 ff 4 SP2 9ED5 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 81
... CLI Clear Interrupt Mask CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ¨ (PC rel PC ← (PC rel ? (Mn ← (PC ← (PC rel ? (Mn ← ← (PC push (PCL) SP ← (SP) – 1; push (PCH) SP ← ...
Page 82
... SP2 9ED3 INH DIR INH INH IX1 SP1 9E6B ff rr DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 83
... LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ Move MOV #opr,opr MOV X+,opr MUL Unsigned multiply MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Description M ← ← ( ← ← ( ← ( ← ( ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← ...
Page 84
... SP1 9E60 IMM DIR EXT IX2 – IX1 SP1 9EEA ff 4 SP2 9EDA DIR INH 49 1 INH 59 1 – – IX1 SP1 9E69 ff 5 DIR INH 46 1 INH 56 1 – – IX1 SP1 9E66 INH MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 85
... SUB opr,SP SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Description A ← (A) – (M) – (C) C ← ← ← (A) (M ← (H:X) I ← 0; Stop Oscillator M ← (X) A ← (A) – (M) PC ← (PC Push (PCL) SP ← ...
Page 86
... Relative program counter offset byte Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 87
Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 88
... Central Processor Unit (CPU) Technical Data 88 Central Processor Unit (CPU) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 89
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Introduction .90 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . .93 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . .93 Clocks in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . .94 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Active Resets from Internal Sources . . . . . . . . . . . . . . . .95 SIM Counter ...
Page 90
... Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation CPU enable/disable timing Modular architecture expandable to 128 interrupt sources System Integration Module (SIM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 91
... RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908MR8 — Rev 4.1 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 7-1. SIM Block Diagram ...
Page 92
... IAB Internal address bus IDB Internal data bus Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal System Integration Module (SIM SBSW Note 1 0 ILOP ILAD 0 LVI Description MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit ...
Page 93
... CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 8. Clock Generator Module CGMXCLK CLOCK A ...
Page 94
... External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address shows the relative timing. System Integration Module (SIM) 7.5 SIM Counter), but an 7.7.4 SIM Reset Status Table 7-2 for details. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 95
... RST as shown in Figure IRST RST CGMXCLK IAB MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Table 7-2. PIN Bit Set Timing Reset Type Number of Cycles Required to set PIN POR/LVI All Others Figure 7-4. External Reset Timing 7-5) ...
Page 96
... CGMXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. System Integration Module (SIM) INTERNAL RESET MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 97
... RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 4096 32 32 CYCLES CYCLES Figure 7-7. POR Recovery 4 – ...
Page 98
... The SIM actively pulls down the RST pin for all internal reset sources. Technical Data 98 voltage falls to the LVI DD LVRX System Integration Module (SIM) voltage and remains at or below that MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 99
... Normal, sequential program execution can be changed in three different ways: 1. Interrupts: 2. Reset 3. Break interrupts MC68HC908MR8 — Rev 4.1 Freescale Semiconductor for counter control and internal reset recovery a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) System Integration Module (SIM) System Integration Module (SIM) SIM Counter 7 ...
Page 100
... Technical Data 100 Figure 7-8 Figure 7-10 shows interrupt recovery timing. 7-9. SP – – – – 4 VECT CCR . Figure 7-8 Interrupt Entry System Integration Module (SIM) shows interrupt entry VECT L START ADDR V DATA H V DATA L OPCODE MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 101
... YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908MR8 — Rev 4.1 Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO INT0 YES INTERRUPT? NO INT1 YES INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS ...
Page 102
... H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Technical Data 102 SP – – – – 1[7:0] PC – 1[15:8] OPCODE A X Figure 7-10. Interrupt Recovery System Integration Module (SIM OPERAND Figure 7-11 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 103
... The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). MC68HC908MR8 — Rev 4.1 Freescale Semiconductor CLI LDA #$FF INT1 ...
Page 104
... Technical Data 104 Figure 7-12 shows the timing for wait mode entry. WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE last instruction. Figure 7-12. Wait Mode Entry Timing System Integration Module (SIM) SAME SAME SAME SAME MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 105
... Figure 7-13 EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt CGMXCLK MC68HC908MR8 — Rev 4.1 Freescale Semiconductor and Figure 7-14 show the timing for wait recovery. IAB $6E0B $6E0C ...
Page 106
... BIt Reserved 1. Writing a logic 0 clears SBSW. Figure 7-15. SIM Break Status Register (SBSR Wait mode was exited by break interrupt Wait mode was not exited by break interrupt. System Integration Module (SIM Bit 0 SBSW (1) Note 0 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 107
... DEC HIBYTE,SP DOLO DEC LOBYTE,SP RETURN PULH RTI MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ; See if wait mode was exited by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT opcode. ; Restore H register. System Integration Module (SIM) ...
Page 108
... Last reset caused by an illegal opcode 0 = POR or read of SRSR 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR System Integration Module (SIM Bit 0 ILAD 0 LVI MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 109
... BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor $FE03 BIt ...
Page 110
... System Integration Module (SIM) Technical Data 110 System Integration Module (SIM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 111
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Introduction .112 Features .112 Functional Description .113 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .113 Phase-Locked Loop Circuit (PLL .115 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . .121 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . .122 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 CGM External Connections ...
Page 112
... Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector Central processor unit (CPU) interrupt on entry or exit from locked condition Clock Generator Module (CGM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 113
... An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor the constant crystal frequency clock, CGMXCLK. programmable VCO frequency clock, CGMVCLK. selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT ...
Page 114
... PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL[7:4] CGMVCLK FREQUENCY DIVIDER Figure 8-1. CGM Block Diagram Clock Generator Module (CGM) CGMXCLK TO SIM A CGMOUT ÷ SIM B S* *WHEN CGMOUT = B USER MODE MONITOR MODE CGMINT MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 115
... The PLL can change between acquisition and tracking modes either automatically or manually. 8.4.2.1 PLL Circuits The PLL consists of these circuits: • • MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Bit 7 6 Read PLLF : PLLIE PLLON ...
Page 116
... Clock Generator Module (CGM) • • • Technical Data 116 Phase detector Loop filter Lock detector Clock Generator Module (CGM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 117
... CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f condition based on this comparison. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor is equal to the nominal center-of-range VRS , (4.9152 MHz) times a linear factor L, or (L) f NOM ...
Page 118
... ACQ bit is set. See Clock Selector Circuit. (8.6.2 PLL Bandwidth Control 8.7 Interrupts for information and precautions on using interrupts. Clock Generator Module (CGM) Register. 8.4.3 Base Register). If PLL interrupts 8.4.3 Base Clock Selector MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 119
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor The ACQ bit (see 8.6.2 PLL Bandwidth Control read-only indicator of the mode of the filter. See Acquisition and Tracking The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆ ...
Page 120
... In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L. Clock Generator Module (CGM) . BUSDES × BUSDES . RCLK × f RCLK ) 4 ⁄ VCLK . NOM to f and VCLK VRS must be within the VCLK , and f must be as close as VRS MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 121
... PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor A 0 value for N is interpreted exactly the same as a value value for L disables the PLL and prevents its selection as the source for the base clock ...
Page 122
... Pierce S also shows the external components for the PLL: Bypass capacitor, C BYP Filter capacitor 8.11 Acquisition/Lock Time Specifications Clock Generator Module (CGM) Figure 8-3 shows only the logical for routing MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 123
... The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, C CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the C MC68HC908MR8 — Rev 4.1 Freescale Semiconductor SIMOSCEN OSC1 OSC2 ...
Page 124
... V carefully for maximum noise immunity and place bypass DDA ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of CGMXCLK to OSC1 and Clock Generator Module (CGM) pin. DD MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 125
... See page 126. PLL Bandwidth Control Reg- $005D ister (PBWC) See page 129. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor PLL control register (PCTL), see PLL bandwidth control register (PBWC), see Bandwidth Control Register PLL programming register (PPG), see Register is a summary of the CGM registers. ...
Page 126
... Technical Data 126 Bit Read : MUL7 MUL6 MUL5 MUL4 Write : Re set Reserved $005C Bit PLLF PLLIE PLLON BCS Reserved Figure 8-5. PLL Control Register (PCTL) Clock Generator Module (CGM Bit 0 VRS7 VRS6 VRS5 VRS4 Bit MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 127
... CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. Reset clears the BCS bit. See MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 1 = PLL interrupts enabled 0 = PLL interrupts disabled 1 = Change in lock condition change in lock condition Circuit ...
Page 128
... CGMVCLK requires two writes to the PLL control register. See PCTL Bits 3–0 — Unimplemented Bits These bits provide no function and always read as logic 1s. Technical Data 128 8.4.3 Base Clock Selector Clock Generator Module (CGM) Circuit. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 129
... VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked ...
Page 130
... These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write 0s to PBWC[3:0] whenever writing to PBWC. Technical Data 130 1 = Tracking mode 0 = Acquisition mode 1 = Crystal reference is not active Crystal reference is active. Clock Generator Module (CGM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 131
... Reset initializes these bits give a default multiply value of 6. NOTE: The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). MC68HC908MR8 — Rev 4.1 Freescale Semiconductor $005E Bit MUL7 MUL6 ...
Page 132
... If the application is not Technical Data 132 . See 8.4.2.1 PLL Circuits, 8.4.2.4 Programming the Register. VRS[7:4] cannot be written when the Exceptions. A value the VCO range for more information. Clock Generator Module (CGM) PLL, and 8.4.2.5 and 8.4.2.5 Special MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 133
... To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit status bit is cleared during the break state, it remains cleared when the MCU exits the break state. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Wait Mode 7 ...
Page 134
... Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. Technical Data 134 Clock Generator Module (CGM) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 135
... Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency, f MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Acquisition time the time the PLL takes to reduce the error ACQ between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆ ...
Page 136
... F V DDA ---------------- - FACT f RDV , see 8.11 Acquisition/Lock Time FACT , choose the voltage potential at DDA Clock Generator Module (CGM) Capacitor. . The DDA Time, the MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 137
... Manual and Automatic PLL Bandwidth clock cycles, n tracking mode entry tolerance, ∆ MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Correct selection of filter capacitor, C Filter Capacitor Room temperature operation Negligible external leakage on CGMXFC Negligible noise is the K factor when the PLL is configured in acquisition mode, and is the K factor when the PLL is configured in tracking mode ...
Page 138
... PLL clock (see may slow the lock time considerably. Clock Generator Module (CGM required to ascertain that the . Therefore, the Lock /f , and the ACQ RDV /f . Also, TRK RDV 8.4.3 Base Clock Selector 8.11.2 Parametric Influences MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 139
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Introduction .140 Features .141 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Resolution .146 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 PWM Generators .148 Load Operation .148 PWM Data Overflow and Underflow Conditions . . . . . .152 Output Control ...
Page 140
... Pulse-Width Modulator for Motor Control (PWMMC) PWM Control Register .177 Dead-Time Write-Once Register . . . . . . . . . . . . . . . . . . .179 PWM Disable Mapping Write-Once Register . . . . . . . . .179 Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 PWM Glossary .185 ) and a programmable prescaler MHz). OP Figure 9-1. Figure 9-2. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 141
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Three complimentary PWM pairs or six independent PWM signals Edge-aligned PWM signals or center-aligned PWM signals PWM signal polarity control ...
Page 142
... LDFQ1 LDFQ0 SEL12 FMODE FINT4 FFLAG FPIN4 FTACK OUTCT OUT6 OUT5 Reserved Bold Bit 0 PWME LDOK SEL34 SEL56 PRSC1 PRSC0 FMODE FINT1 FFLAG 0 0 FPIN1 FTACK OUT4 OUT3 OUT2 OUT1 Bit 11 Bit 10 Bit 9 Bit Buff- ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 143
... See page 174. PWM 2 Value Register $002D Low (PVAL2L) See page 174 Unaffected X = Indeter- minate Figure 9-2. Register Summary (Sheet MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Bit Read: Bit 7 Bit 6 Bit 5 ...
Page 144
... Bit 13 Bit Reserved Bold Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Buff- ered MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 145
... PWM Disable Mapping Write-Once Register $0037 (DISMAP) See page 179 Unaffected X = Indeter- minate Figure 9-2. Register Summary (Sheet MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Bit Read: Bit 7 Bit 6 Bit 5 ...
Page 146
... The up/down counter uses the value in the timer modulus (timer modulus) x (PWM clock period 9-4. Again, the timer modulus register is used to determine the (timer modulus) x (PWM clock period) 5.4 CONFIG = 8 MHz) as shown MHz) as shown in OP Bits. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 147
... MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MODULUS = 4 PERIOD = 8 x (PWM CLOCK PERIOD) PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 Figure 9-3. Center-Aligned PWM (Positive Polarity) UP-ONLY COUNTER MODULUS = 4 PWM = 0 ...
Page 148
... PWM parameters in real time for the PWM module. Technical Data 148 Pulse-Width Modulator for Motor Control (PWMMC) Table 9-1. PWM Prescaler Prescaler Bits PWM Clock Frequency PRSC1:PRSC0 Table 9-2. When a reload cycle arrives, Table 9-1 shows how MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 149
... When the PWMINT bit is clear, PWM interrupt requests are inhibited. PWM reloads will still occur at the reload rate, but no interrupt requests will be generated. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Table 9-2. PWM Reload Frequency ...
Page 150
... PWMF SET PWMF SET PWMF SET PWM Figure 9-7. Center-Aligned PWM Value Loading READ PWMF AS 1, WRITE PWMF RESET PWMF CPU INTERRUPT REQUEST PWMINT 9-7, Figure 9-8, Figure 9-9, and LDOK = 0 MODULUS = 3 PWM VALUE= 1 PWMF SET MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 151
... UP/DOWN COUNTER PWM MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) LDOK = 1 LDOK = 1 MODULUS = 3 MODULUS = 2 PWM VALUE= 1 PWM VALUE = 1 PWMF SET PWMF SET Figure 9-8. Center-Aligned Loading of Modulus ...
Page 152
... Normal $1000–$7FFF Overflow $8000–$FFFF Underflow 5.4 CONFIG 9-12. Figure 9-4, if the PWM value is Table PWM Value Used Per registers contents $FFF $000 Bits). If complementary operation Figure 9-11. Operation MC68HC908MR8 — Rev 4.1 Freescale Semiconductor 9-3. ...
Page 153
... If independent operation is chosen, each PWM has its own PWM value register. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) PWMS 1 & 2 PWMS 3 & 4 PWMS 5 & 6 Figure 9-11. Complementary Pairing ...
Page 154
... PWM generator outputs, are fed into the dead-time generators. See 9.6.4 Output Port Control Technical Data 154 Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-12, in complementary mode, each PWM pair can 9-12, if PWM1 and PWM2 were on at the same time, large Register. Figure 9-13. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 155
... Figure duty cycle boundaries (near 0% and 100% duty cycles). shows the effects of dead-time insertion on pulse widths smaller than the dead-time. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) OUT2 OUT4 OUT6 ...
Page 156
... PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME = 2 PWM2 W/ 2 DEAD-TIME = 2 Figure 9-15. Dead-Time at Duty Cycle Boundaries Technical Data 156 Pulse-Width Modulator for Motor Control (PWMMC) PWM VALUE = PWM VALUE = 1 PWM VALUE = PWM VALUE = PWM VALUE = 3 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 157
... This reduces the chances of the software inadvertently changing the polarity of the PWM signals and possibly damaging the motor drive hardware. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) PWM VALUE = 3 ...
Page 158
... Technical Data 158 Pulse-Width Modulator for Motor Control (PWMMC) UP-ONLY COUNTER EDGE-ALIGNED NEGATIVE POLARITY UP-ONLY COUNTER MODULUS = 4 Figure 9-17. PWM Polarity EDGE-ALIGNED POSITIVE POLARITY MODULUS = 4 PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 159
... In addition, if complementary operation is in use, the PWM pairs will not be allowed to be active simultaneously, and dead-time will still not be violated. When OUTCTL is set and MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-18 ...
Page 160
... Figure 9-19. Dead-Time Insertion During OUTCTL = 1 Technical Data 160 Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-14. Dead-time is inserted Figure 9-20. 2 DEAD-TIME INSERTED DUE TO SETTING OF OUT1 BIT Figure 9-19. Although 2 DEAD-TIME INSERTED DUE TO CLEARING OF OUT1 BIT MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 161
... While the PWM pins are disabled, they are forced to their inactive state. The PWM generator continues to run — only the output pins are disabled MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) 2 ...
Page 162
... S Q FFLAG4 MANUAL MODE R FINT4 CYCLE START FMODE1 AUTO FPIN1 MODE ONE S Q SHOT FFLAG1 MANUAL MODE R FINT1 SOFTWARE X DISABLE BANK Y DISABLE FAULT PIN 4 DISABLE INTERRUPT REQUEST FAULT PIN 1 DISABLE S Q BANK X DISABLE R INTERRUPT REQUEST MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 163
... A fault can also generate a CPU interrupt. Each fault pin has its own interrupt vector. Ad- dress: Read: Write: Reset: Figure 9-22. PWM Disable Mapping Write-Once Register (DISMAP) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-22 and Figure 9-23 $0037 Bit 7 6 ...
Page 164
... Pulse-Width Modulator for Motor Control (PWMMC) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 9-23. PWM Disabling Decode Scheme DISABLE PWM PIN 1 DISABLE PWM PIN 2 DISABLE PWM PIN 3 DISABLE PWM PIN 4 DISABLE PWM PIN 5 DISABLE PWM PIN 6 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 165
... PWM cycle begins as shown in event bit will not enable the PWMs in automatic mode. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-24 ...
Page 166
... Figure 9-24. PWM Disabling in Automatic Mode The FFLAGx bit is cleared by writing the corresponding FTACKx bit. The FINTx bit is cleared. (This will not clear the FFLAGx bit.) Reset — A reset automatically clears all four interrupt latches. PWM(S) ENABLED MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 167
... PWM(s) to enable, only if a logic low level at the fault pin is present at the start of a PWM cycle. See MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-26 ...
Page 168
... DISABLE BIT Technical Data 168 Pulse-Width Modulator for Motor Control (PWMMC) Figure 9-27. Setting a PWM disable bit does not latch a CPU PWM(S) DISABLED PWM(S) ENABLED Figure 9-27. PWM Software Disable PWM(S) ENABLED MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 169
... PWM values, polarity, and dead-time. See the timing diagram in CPU CLOCK PWMEN HI-Z IF OUTCTL = 0 PWM PINS MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Registers. Figure DRIVE ACCORDING TO PWM VALUE, POLARITY, AND DEAD-TIME Figure 9-28 ...
Page 170
... Internally, the PWM generator will force its outputs avoid glitches when the PWMEN is set again. All fault circuitry Manual PWM pin control via the PWMOUT register Dead-time insertion when PWM pins change via the PWMOUT register MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 171
... PWMF and FFLAGx bits. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) PWM Operation in Break Mode Register ...
Page 172
... Pulse-Width Modulator for Motor Control (PWMMC) $0026 Bit Unimplemented Figure 9-29. PWM Counter Register High (PCNTH) $0027 Bit Bit 7 Bit 6 Bit 5 Bit Unimplemented Figure 9-30. PWM Counter Register Low (PCNTH Bit 0 Bit11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 173
... If a modulus loaded, the counter will continually count down from $FFF. This operation will not be tested or guaranteed. (The user should consider it MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) $0028 ...
Page 174
... Pulse-Width Modulator for Motor Control (PWMMC) Bit Bit 15 Bit 14 Bit 13 Bit Figure 9-33. PWMx Value Registers High (PVALxH) Bit Bit 7 Bit 6 Bit 5 Bit Figure 9-34. PWMx Value Registers Low (PVALxL Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 175
... This read/write bit allows the user to enable and disable PWM CPU interrupts. If set, a CPU interrupt will be pending when the PWMF flag is set. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) $0020 ...
Page 176
... Okay to load new modulus, prescaler, and PWM values at beginning of next PWM load cycle 0 = Not okay to load new modulus, prescaler, and PWM values Bit PWM generator and PWM pins enabled 0 = PWM generator and PWM pins disabled 9.8 Initialization MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 177
... NOTE: When reading these bits, the value read is the buffer value (not necessarily the value the PWM generator is currently using). MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) $0021 Bit 7 ...
Page 178
... Use PWM value register Use PWM value register Use PWM value register Use PWM value register Use PWM value register Use PWM value register 5. Table 9-6. Table 9-6. PWM Prescaler Prescaler Bits PRSC1:PRSC0 PWM Clock Frequency MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 179
... Ad- dress: Read: Write: Reset: Figure 9-38. PWM Disable Mapping Write-Once Register (DISMAP) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) $0036 Bit Bit 7 Bit 6 ...
Page 180
... FMODE FINT4 Unimplemented Figure 9-39. Fault Control Register (FCR) Protection Automatic mode 0 = Manual mode 1 = Fault pin 1 will cause CPU interrupts Fault pin 1 will not cause CPU interrupts. Protection Automatic mode 0 = Manual mode Bit 0 FMODE FINT1 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 181
... FPIN1 — State of Fault Pin 1 This read-only bit allows the user to read the current state of fault pin 1. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC Fault pin 4 will cause CPU interrupts. ...
Page 182
... Technical Data 182 Pulse-Width Modulator for Motor Control (PWMMC fault has occurred on fault pin new fault on fault pin Fault pin logic Fault pin logic 0. $0024 Bit FTACK Unimplement- ed Figure 9-41. Fault Acknowledge Register (FTACK Bit FTACK MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 183
... The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit will always read 0. Writing this bit will clear FFLAG4. Writing a 0 will have no effect. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Control Logic Block ...
Page 184
... Pulse-Width Modulator for Motor Control (PWMMC) $0025 Bit OUT- OUT6 OUT5 CTL Unimplement- ed Figure 9-42. PWM Output Control Register (PWMOUT PWM outputs controlled manually 0 = PWM outputs determined by PWM generator Bit 0 OUT4 OUT3 OUT2 OUT1 Unaffected MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 185
... PWM Clock Cycle (or Period) — One tick of the PWM counter (1/f with no prescaler). See PWM Cycle (or Period) • • MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) Pulse-Width Modulator for Motor Control (PWMMC) Table 9-7. OUTx Bits Complementary Mode 1 — PWM1 is active 0 — ...
Page 186
... EDGE-ALIGNED MODE PWM CLOCK CYCLE PWM CYCLE (OR PERIOD) LDFQ1:LDFQ0 = 01 — RELOAD EVERY TWO CYCLES PWM LOAD CYCLE (1/PWM LOAD FREQUENCY) Figure 9-44. PWM Load Cycle/Frequency Definition Figure 9-44. RELOAD NEW MODULUS, PRESCALER, AND PWM VALUES IF LDOK = 1 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 187
... Features Features of the monitor ROM include: • • • • MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction .187 Features .187 Functional Description .188 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . .188 Forced Monitor Mode .190 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Data Format ...
Page 188
... Disabled 0 until reset = V PLL configured with BCS set by monitor code PLL configured with BCS set by monitor code Enters monitor mode with any f OSC /4 Disabled external clock rate /1024 within operating spec X Enabled X Enters user mode MC68HC908MR8 — Rev 4.1 Freescale Semiconductor DD ...
Page 189
... MC145407 + 10 µ µ DB- MC68HC908MR8 — Rev 4.1 Freescale Semiconductor V DDA 0.1 µ µ µ Figure 10-1. Monitor Mode Circuit Monitor ROM (MON) Monitor ROM (MON) Functional Description V DD MC68HC908MR8 10 kΩ RST 0.1 µ kΩ IRQ V DDA V SSA V REFH V REFH 0.1 µF CGMXFC 0.02 µ ...
Page 190
... Vector Low Enabled $FFFE $FFFF (1) $FEFE $FEFF Disabled ) is removed from the IRQ pin or the RST pin, the SIM HI Monitor ROM (MON) for more information on , the HI SWI SWI Vector High Vector Low $FFFC $FFFD $FEFC $FEFD MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 191
... Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. See $A5 BREAK The data transmit and receive rate is 9600 baud. Transmit and receive baud rates will be identical. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Table 10-1, on FLASH parts when V Timing. START BIT 0 BIT 1 ...
Page 192
... ROM immediately echoes each READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW Figure 10-4. Read Transaction MISSING STOP BIT Figure 10-5. Break Transaction Monitor ROM (MON) ADDR. LOW DATA RESULT Figure 10-5. TWO-STOP-BIT DELAY BEFORE ZERO ECHO MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 193
... Data returned None Opcode $49 Command sequence SENT TO MONITOR WRITE WRITE ECHO MC68HC908MR8 — Rev 4.1 Freescale Semiconductor READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer RUN, run user program Table 10-3 through Table READ ADDR ...
Page 194
... Command sequence SENT TO MONITOR ECHO NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. Technical Data 194 IREAD IREAD DATA IWRITE IWRITE DATA Monitor ROM (MON) DATA RESULT DATA MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 195
... Table 10-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data returned None Opcode $28 Command sequence MC68HC908MR8 — Rev 4.1 Freescale Semiconductor READSP READSP SP HIGH SENT TO MONITOR RUN RUN ECHO Monitor ROM (MON) Monitor ROM (MON) Functional Description ...
Page 196
... Wait 1 bit time before sending next byte. Technical Data 196 4096 + 32 CGMXCLK CYCLES 24 BUS CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST FROM MCU Figure 10-6. Monitor Mode Entry Timing Monitor ROM (MON) D). If the X Figure 10- MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 197
... After failing the security sequence, the FLASH memory can also be bulk erased by executing an erase routine that was downloaded into internal RAM. The bulk erase operation clears the security code locations so that all eight security bytes become $FF. MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Monitor ROM (MON) Monitor ROM (MON) Security Technical Data ...
Page 198
... Monitor ROM (MON) Technical Data 198 Monitor ROM (MON) MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...
Page 199
... TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .216 11.10.3 TIMA Counter Modulo Registers .217 11.10.4 TIMA Channel Status and Control Registers .218 11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .222 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Section 11. Timer Interface A (TIMA) Introduction .200 Features .200 Functional Description .204 TIMA Counter Prescaler ...
Page 200
... External TIMA clock input (4-MHz maximum frequency) Free-running or modulo up-count operation Toggle any channel pin on overflow TIMA counter stop and reset bits Timer Interface A (TIMA) Figure 11-2 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor ...