MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet

IC MCU 12K FLASH 4/8MHZ 64-QFP

MC908LJ12CFUE

Manufacturer Part Number
MC908LJ12CFUE
Description
IC MCU 12K FLASH 4/8MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ12CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ12CFUE
Manufacturer:
FREESCALE
Quantity:
4 330
Part Number:
MC908LJ12CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908LJ12CFUE
Manufacturer:
FREESCALE
Quantity:
4 330
Part Number:
MC908LJ12CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ12
Technical Data
M68HC08
Microcontrollers
Rev. 2.1
MC68HC908LJ12/D
August 2, 2005
freescale.com

Related parts for MC908LJ12CFUE

MC908LJ12CFUE Summary of contents

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MC68HC908LJ12 Technical Data M68HC08 Microcontrollers Rev. 2.1 MC68HC908LJ12/D August 2, 2005 freescale.com ...

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...

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... Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc Equal Opportunity/Affirmative Action Employer. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Technical Data © Freescale, Inc., 2002 Technical Data 3 ...

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... For your convenience, the page number designators have been linked to the appropriate location. Revision Date Level February 2 First general release. 2002 August, 2005 2.1 Updated to meet Freescale identity guidelines. Technical Data 4 Revision History Description Technical Data Page Number(s) — — MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... Section 15. Analog-to-Digital Converter (ADC 301 Section 16. Liquid Crystal Display Driver (LCD 317 Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 341 Section 18. External Interrupt (IRQ 357 Section 19. Keyboard Interrupt Module (KBI 363 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Interface Module (IRSCI 227 List of Sections List of Sections Technical Data 5 ...

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... List of Sections Section 20. Computer Operating Properly (COP 371 Section 21. Low-Voltage Inhibit (LVI 377 Section 22. Break Module (BRK 383 Section 23. Electrical Specifications 391 Section 24. Mechanical Specifications . . . . . . . . . . . . . 407 Section 25. Ordering Information . . . . . . . . . . . . . . . . . 411 Technical Data 6 MC68HC908LJ12 List of Sections Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power Supply Pins (V DD Analog Power Supply Pin (V Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST) ...

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... FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 64 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 65 FLASH Program Operation .66 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 68 Section 5. Configuration Registers (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Wait Mode ...

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... CGM CPU Interrupt (CGMINT 117 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .120 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . 122 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .123 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 124 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . . 116 ) . . . . . . . . . . . . . . . . . . . . . 116 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Interrupts .125 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 CGM During Break Interrupts 126 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 127 Acquisition/Lock Time Definitions .127 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 127 Choosing a Filter ...

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... Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Security 169 ROM-Resident Routines 171 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 MON_PRGRNGE 177 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 EE_READ 183 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... TIM Channel Status and Control Registers . . . . . . . . . . . . 204 11.10.5 TIM Channel Registers 207 12.1 12.2 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 11. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Input Capture ...

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... Month Register (MTHR .225 Section 13. Infrared Serial Communications Interface Module (IRSCI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Infrared Functional Description 232 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... SCI Data Register (SCDR 263 13.11.7 SCI Baud Rate Register (SCBR 264 13.11.8 SCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . . . . 267 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Character Transmission ...

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... Clock Phase and Polarity Controls 275 Transmission Format When CPHA = 276 Transmission Format When CPHA = 278 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 279 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Interrupts .286 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 15. Analog-to-Digital Converter (ADC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Monotonicity ...

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... Port 347 Port B Data Register (PTB 347 Data Direction Register B (DDRB 348 Port B LED Control Register (LEDB 350 Port 351 Port C Data Register (PTC 351 Data Direction Register C (DDRC 352 Table of Contents , 323 LCD2 LCD3 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 370 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Port 354 Port D Data Register (PTD 354 Data Direction Register D (DDRD 355 Section 18. External Interrupt (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 IRQ Pin ...

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... Section 21. Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 Interrupt LVI Operation 380 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .380 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 380 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 LVI Status Register 381 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 Section 22. Break Module (BRK) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 386 CPU During Break Interrupts ...

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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 52-Pin Low-Profile Quad Flat Pack (LQFP 408 64-Pin Low-Profile Quad Flat Pack (LQFP 409 64-Pin Quad Flat Pack (QFP 410 Section 25. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Table of Contents MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Title MC68HC908LJ12 Block Diagram 64-Pin QFP and 64-Pin LQFP Pin Assignment . . . . . . . . . . . . 38 52-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .46 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 62 FLASH Control Register (FLCR) ...

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... SIM I/O Register Summary .134 CGM Clock Signals 135 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 List of Figures Page MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... Hour Register (HRR 224 12-11 Day Register (DAYR 224 12-12 Month Register (MTHR 225 12-13 Year Register (YRR 225 12-14 Day-Of-Week Register (DOWR 226 12-15 Chronograph Data Register (CHRR 226 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 25 ...

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... SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 287 14-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-13 SPI Control Register (SPCR 294 14-14 SPI Status and Control Register (SPSCR 296 14-15 SPI Data Register (SPDR 299 Technical Data 26 Title MC68HC908LJ12 List of Figures Page Rev. 2.1 — Freescale Semiconductor ...

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... Data Direction Register A (DDRA 345 17-4 Port A I/O Circuit 346 17-5 Port B Data Register (PTB 347 17-6 Data Direction Register B (DDRB 349 17-7 Port B I/O Circuit 349 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Title 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . 333 List of Figures List of Figures Page Technical Data 27 ...

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... SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24-1 52-Pin Low-Profile Quad Flat Pack (Case No. 848D 408 24-2 64-Pin Low-Profile Quad Flat Pack (Case No. 840F 409 24-3 64-Pin Quad Flat Pack (Case No. 840B 410 Technical Data 28 Title MC68HC908LJ12 List of Figures Page Rev. 2.1 — Freescale Semiconductor ...

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... ERARNGE Routine 175 10-13 LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 10-14 MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10-15 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Title Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .120 PRE 1 and PRE0 Programming ...

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... LCD Bias Voltage Control 336 16-2 Resistor Ladder Selection 336 16-4 Fast Charge Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . 337 16-5 LCD Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16-6 LCD Waveform Base Clock Selection . . . . . . . . . . . . . . . . . . 338 Technical Data 30 Title MC68HC908LJ12 List of Tables Page Rev. 2.1 — Freescale Semiconductor ...

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... Oscillator Specifications 398 23-10 ADC 5.0V Electrical Characteristics . . . . . . . . . . . . . . . . . . . .399 23-11 ADC 3.3V Electrical Characteristics . . . . . . . . . . . . . . . . . . . .400 23-12 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 406 25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Title List of Tables List of Tables Page Technical Data 31 ...

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... List of Tables Technical Data 32 MC68HC908LJ12 List of Tables Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power Supply Pins (V DD Analog Power Supply Pin (V Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ) ...

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... Serial communications interface module (SCI) with infrared (IR) encoder/decoder 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 34 General Description 1 feature MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Serial peripheral interface module (SPI) IRQ external interrupt pin with integrated pullup 8-bit keyboard wakeup port with programmable pullup 32 general-purpose input/output (I/O) pins: – High current 8-mA sink capability on PTB2–PTB5 – High current 20-mA sink capability on PTB0–PTB1 ...

Page 36

... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 Technical Data 36 shows the structure of the MC68HC908LJ12. General Description MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 37

... MODULE VDDA VDD POWER VSS VREFH ADC REFERENCE VREFL Figure 1-1. MC68HC908LJ12 Block Diagram MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor INTERNAL BUS KEYBOARD INTERRUPT MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE ...

Page 38

... PTD6/KBI6 11 PTD7/KBI7 12 FP9 13 FP10 14 FP11 15 FP12 16 Figure 1-2. 64-Pin QFP and 64-Pin LQFP Pin Assignment Technical Data 38 General Description VREFL 48 VREFH 47 PTB7/ADC5 46 PTB6/ADC4 45 PTA7/ADC3 44 PTA6/ADC2 43 PTA5/ADC1 42 PTA4/ADC0 41 PTA3/KBI3 40 PTA2/KBI2 39 PTA1/KBI1 38 PTA0/KBI0 37 PTC7/FP26 36 PTC6/FP25 35 PTC5/FP24 34 PTD0/SS 33 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 39

... FP11 12 FP12 13 Pins not available on 52-LQFP package: PTB7ADC5 PTB6/ADC4 PTB5/T2CH1 PTB4/T2CH0 Internal pads are unconnected. Figure 1-3. 52-Pin LQFP Pin Assignment MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor PTD7/KBI7 PTD6/KBI6 PTD5/KBI5 PTD4/KBI4 PTD3/SPSCK PTD2/MOSI PTD1/MISO PTD0/SS General Description General Description VREFL 39 VREFH ...

Page 40

... DDA MCU 0.1 µF C1(a) + C2(a) NOTE: Component values shown V DD represent typical applications. Figure 1-4. Power Supply Bypassing General Description Figure 1-4 must be grounded for SS . For maximum noise DD Figure 1-4). V DDA 0.1 µF C1(b) + C2( MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 41

... Section 15. Analog-to-Digital Converter (ADC) 1.6.8 ADC Voltage Low Reference Pin (V V REFL Section 15. Analog-to-Digital Converter (ADC) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor (SIM). Section 18. External Interrupt ) REFH is the voltage input pin for the ADC voltage high reference. See ) REFL is the voltage input pin for the ADC voltage low reference. See ...

Page 42

... BP0–BP2 are the LCD backplane driver pins and FP1– FP18 are the frontplane driver pins. FP0/BP3 is the shared driver pin between FP0 and BP3 Technical Data 42 16.). (Section 16.). General Description (Section 17.). (Section 15.), and (Section 19.). (Section 17.). (Section 13.), (Section 11.), TIM1(Section 11.), (Section 15.). (Section 17.). (Section 17.). (Section 19.). (Section 14.). MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 43

... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 43 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input/Output (I/O) Section Figure 2-1, includes: ...

Page 44

... LVI status register, LVISR • $FFFF; COP control register, COPCTL Data registers are shown in locations. Technical Data 44 Figure 2-1 and in register figures in this document, Figure 2-2. Table 2-1 MC68HC908LJ12 Memory Map is a list of vector Rev. 2.1 — Freescale Semiconductor ...

Page 45

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $0000 I/O Registers ↓ $005F $0060 ↓ 512 Bytes $025F $0260 Unimplemented ↓ 48,544 Bytes $BFFF $C000 FLASH Memory ↓ 12,288 Bytes $EFFF $F000 Unimplemented ↓ 3,072 Bytes $FBFF $FC00 Monitor ROM 1 ↓ 512 Bytes ...

Page 46

... Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 47

... Reset: Read: SPI Data Register $0012 Write: (SPDR) Reset: Read: SCI Control Register 1 $0013 Write: (SCC1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit LEDB5 LEDB4 SPRIE R SPMSTR CPOL SPRF ...

Page 48

... Unimplemented Memory Map Bit RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 TNP1 TNP0 IREN KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 PCEH PCEL LVISEL1 LVISEL0 †† †† Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 49

... Timer 1 Channel 0 Status $0025 and Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 $0026 Register High Write: (T1CH0H) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit COPRS LVISTOP LVIRSTD LVIPWRD TOF TOIE TSTOP ...

Page 50

... TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Unimplemented Memory Map Bit Bit ELS1B ELS1A TOV1 CH1MAX Bit Bit PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 51

... Read: PLL Multiplier Select $0039 Register Low Write: (PMSL) Reset: Read: PLL VCO Range Select $003A Register Write: (PMRS) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit Bit Bit CH1F 0 CH1IE ...

Page 52

... HRF Unimplemented Memory Map Bit 0 RDS3 RDS2 RDS1 RDS0 ADCH3 ADCH2 ADCH1 ADCH0 ADx ADx ADx ADx ADx ADx ADx ADx MODE1 MODE0 MINIE SECIE TB1IE TB2IE XTL2 XTL1 XTL0 MINF SECF TB1F TB2F Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 53

... Write: (YRR) Reset: Read: Day-Of-Week Register $004D Write: (DOWR) Reset: Read: Chronograph Data $004E Register Write: (CHRR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit AM5 AM4 AH4 SEC5 SEC4 ...

Page 54

... LCLK1 LCLK0 LCCON3 LCCON2 LCCON1 LCCON0 F0B3 F0B2 F0B1 F0B0 F2B3 F2B2 F2B1 F2B0 F4B3 F4B2 F4B1 F4B0 F6B3 F6B2 F6B1 F6B0 F8B3 F8B2 F8B1 F8B0 F10B3 F10B2 F10B1 F10B0 F12B3 F12B2 F12B1 F12B0 Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 55

... Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit F15B3 F15B2 F15B1 F15B0 F17B3 F17B2 F17B1 F17B0 ...

Page 56

... R 0 IF6 IF5 IF4 IF3 IF14 IF13 IF12 IF11 BPR7 BPR6 BPR5 BPR4 Unimplemented Memory Map Bit IF2 IF1 IF10 IF9 IF8 IF7 IF17 IF16 IF15 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 57

... Reset: Read: LVIOUT Low-Voltage Inhibit Status $FE0F Register Write: (LVISR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit Bit Bit BRKE BRKA 0 ...

Page 58

... IF2 $FFF9 LVI Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) Memory Map Vector MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 59

... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Random-Access Memory (RAM) Technical Data 59 ...

Page 60

... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 60 Random-Access Memory (RAM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 61

... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 4. FLASH Memory (FLASH) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 64 FLASH Mass Erase Operation ...

Page 62

... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 62 Bit BPR7 BPR6 BPR5 BPR4 Unimplemented FLASH Memory (FLASH Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 63

... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $FE08 Bit ...

Page 64

... RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Technical Data 64 (at least 10µs). nvs (1ms). erase (5µs). nvh (1µs), the memory can be accessed again in read rcv FLASH Memory (FLASH) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 65

... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor register. address range. (10µs). nvs (4ms). ...

Page 66

... FLASH memory. Technical Data 66 (10µs). nvs (5µs). pgs (30µs). prog (5µs). nvh (1µs), the memory can be accessed again in read rcv maximum. See 23.18 FLASH Memory prog shows a flowchart representation for programming the FLASH Memory (FLASH) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 67

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t ...

Page 68

... Start address of FLASH block protect Technical Data 68 $FE09 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-4. FLASH Block Protect Register (FLBPR Figure 4-5. FLASH Block Protect Start Address FLASH Memory (FLASH Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address BPR[7:1] MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 69

... XX00 or XX80 (at page boundaries — 128 bytes) within the FLASH memory. Examples of protect start address: MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor BPR[7:0] Start of Address of Protect Range $00 or $01 The entire FLASH memory is protected. $02 or $03 $04 or $05 ...

Page 70

... FLASH Memory (FLASH) Technical Data 70 FLASH Memory (FLASH) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 71

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2 Computer operating properly module (COP) 18 COP timeout period (2 – 2 Low-voltage inhibit (LVI) module power LVI module reset LVI module in stop mode ...

Page 72

... Technical Data 72 Bit STOP_ STOP_ DIV2CLK IRCDIS XCLKEN COPRS LVISTOP LVIRSTD LVIPWRD Unimplemented Figure 5-2 Configuration Registers (CONFIG Bit 0 PCEH PCEL LVISEL1 LVISEL0 †† †† SSREC STOP COPD and Figure 5-3. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 73

... LVIRSTD — LVI Reset Disable LVIRSTD disables the reset signal from the LVI module. (See Section 21. Low-Voltage Inhibit LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. (See Inhibit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $001F Bit COPRS LVISTOP LVIRSTD LVIPWRD 0 0 ...

Page 74

... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See Operating Properly 1 = COP module disabled 0 = COP module enabled Technical Data 74 (COP).) Configuration Registers (CONFIG) Section 20. Computer MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 75

... CGM module; CGMOUT will equal CGMXCLK and bus clock will equal CGMXCLK divide-by-2. DIV2CLK bit has no effect when the BCS=1 in the PLL control register (CGMVCLK selected and divide-by-2 always enabled). Reset clears this bit. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $001D Bit STOP_ STOP_ ...

Page 76

... PTC0–PTC3 Section 21. Low-Voltage Inhibit for the LVI voltage trip points for each of LVISEL1 LVISEL0 Table 5-1. LVI Trip Point Selection Configuration Registers (CONFIG) (LVI).) The voltage mode . See Section 23. DD Operating Mode Reserved (2.5V Reserved MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 77

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Stop Mode ...

Page 78

... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes • Low-power stop and wait modes Technical Data 78 Central Processor Unit (CPU) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 79

... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor shows the five CPU registers. CPU registers are not part Figure 6-1. CPU Registers ...

Page 80

... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: Technical Data 80 Bit Indeterminate Figure 6-3. Index Register (H:X) Bit Figure 6-4. Stack Pointer (SP) Central Processor Unit (CPU) Bit Bit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 81

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit Loaded with Vector from $FFFE and $FFFF Figure 6-5 ...

Page 82

... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 82 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 83

... Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result ...

Page 84

... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock. Technical Data 84 Central Processor Unit (CPU) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 85

... The opcode map is provided in MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock. ...

Page 86

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 87

... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...

Page 88

... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 89

... Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP EOR opr,SP MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – ...

Page 90

... SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 44 1 INH 54 1 IX1 SP1 9E64 ff 5 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 91

... Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP RSP Reset Stack Pointer MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← ...

Page 92

... SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 SP2 9ED0 ee ff MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 93

... Indexed, 16-bit offset addressing mode M Memory location N Negative bit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

Page 94

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 ...

Page 95

... MCU sub-systems. The oscillator module consist of two types of oscillator circuits: • • MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Crystal (X-tal) Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2 Oscillator Enable Signal (SIMOSCEN) ...

Page 96

... Figure 7-1. Oscillator Module Block Diagram Technical Data 96 7-1. shows the block diagram of the oscillator module. EN INTERNAL RC OSCILLATOR OSC1 OSC2 Oscillator (OSC) ICLK To SIM, COP CGMRCLK To CGM PLL CGMXCLK To RTC, ADC, LCD, CGM Clock Selection MUX MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 97

... Refer to the crystal manufacturer’s data for more information. 7.5 I/O Signals The following paragraphs describe the oscillator I/O signals. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor = 5V) that requires no external components the reference clock Crystal Fixed capacitor Tuning capacitor, C ...

Page 98

... This is buffered signal of CGMXCLK used by the CGM as the phase-locked-loop (PLL) reference clock. 7.6 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Technical Data 98 for detail specification of the MC68HC908LJ12 Oscillator (OSC) Rev. 2.1 — Freescale Semiconductor ...

Page 99

... To disable the ICLK in stop mode, set the STOP_IRCDIS bit to logic 1 before entering stop mode. 7.7 Oscillator During Break Mode The oscillator circuits continue to drive CGMXCLK, CGMRCLK, and ICLK when the device enters the break state. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Oscillator (OSC) Oscillator (OSC) Technical Data 99 ...

Page 100

... Oscillator (OSC) Technical Data 100 MC68HC908LJ12 Oscillator (OSC) Rev. 2.1 — Freescale Semiconductor ...

Page 101

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Phase-Locked Loop Circuit (PLL 106 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . 108 Manual and Automatic PLL Bandwidth Modes 108 Programming the PLL ...

Page 102

... Interrupts .125 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 CGM During Break Interrupts 126 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 127 Acquisition/Lock Time Definitions .127 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 127 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Clock Generator Module (CGM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 103

... Figure 8-1 Figure 8-2 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low-frequency crystal operation with low-power operation and high-output frequency resolution Programmable prescaler for power-of-two increases in frequency Programmable hardware voltage-controlled oscillator (VCO) for ...

Page 104

... DIVIDER CGMPCLK Figure 8-1. CGM Block Diagram Clock Generator Module (CGM) To SIM (and COP) T0 RTC, ADC, LCD USER MODE: CGMOUT = B RESET: A CGMOUT A ÷ SIM SIMDIV2 BASE From SIM CLOCK SELECT CIRCUIT DIV2CLK CONFIG2 CGMINT To SIM MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 105

... When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 8-2. CGM I/O Register Summary MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit PLLF PLLIE PLLON ...

Page 106

... Frequency pre-scaler • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector Technical Data 106 for detailed description on oscillator Section 12. Real Time Clock (RTC) Clock Generator Module (CGM) for detailed MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 107

... CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f condition based on this comparison. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor is equal to the nominal center-of-range VRS , (38.4 kHz) times a linear factor, L, and a power-of-two NOM E )f ...

Page 108

... Technical Data 108 8.6.2 PLL Bandwidth Control 8.4.8 Base Clock Selector 8.6.2 PLL Bandwidth Control for information and precautions on using interrupts.) Clock Generator Module (CGM) Register.) Circuit.) The PLL is Register.) If PLL 8.4.8 Base Clock Selector MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 109

... Such systems typically operate well below f BUSMAX MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor The ACQ bit (See 8.6.2 PLL Bandwidth Control read-only indicator of the mode of the filter. (See Acquisition and Tracking The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance ...

Page 110

... The VCO frequency must be an integer multiple of this rate. Technical Data 110 (See 8.9 Acquisition/Lock Time ACQ AL P × VCLKDES CGMPCLK Clock Generator Module (CGM) , after entering tracking mode . BUSDES . VCLKDES × P × BUSDES , and the RCLK /R. For RCLK MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 111

... Calculate N: 5. Calculate and verify the adequacy of the VCO and bus MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor The relationship between the VCO frequency, f reference frequency, f RCLK f VCLK where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, ...

Page 112

... NOM ≤ – -------------------------- f f VRS VCLK . For proper operation, f VCLKDES VCLKDES VCLK. Clock Generator Module (CGM 38.4kHz NOM    f NOM NOM E × VCLK VRS must be within the VCLK , and f must be as close as VRS MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 113

... MHz 32 MHz MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent the VPR bits of the PLL control register (PCTL), program the binary equivalent the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N ...

Page 114

... PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock. Technical Data 114 8.4.6 Programming the PLL Circuit.) Clock Generator Module (CGM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 115

... PLL performance.) 8.5 I/O Signals The following paragraphs describe the CGM I/O signals. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor shows the external components for the PLL: Bypass capacitor, C BYP Filter network 8.9 Acquisition/Lock Time Specifications ...

Page 116

... DDA ) SSA pin to the same voltage potential as the V carefully for maximum noise immunity and place bypass SSA is physically bonded to the V SSA Clock Generator Module (CGM) pin. DD pin. SS pin. SS MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 117

... The following registers control and monitor operation of the CGM: • • • • • MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor PLL control register (PCTL) (See 8.6.1 PLL Control Register.) PLL bandwidth control register (PBWC) (See 8.6.2 PLL Bandwidth Control PLL multiplier select registers (PMSH and PMSL) (See 8 ...

Page 118

... Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. Technical Data 118 $0036 Bit PLLF PLLIE PLLON BCS Unimplemented Figure 8-4. PLL Control Register (PCTL) Clock Generator Module (CGM Bit 0 PRE1 PRE0 VPR1 VPR0 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 119

... These prescaler bits affects the relationship between the VCO clock and the final system bus clock. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 1 = PLL PLL off Circuit.) Reset clears the BCS bit CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT 8 ...

Page 120

... Table 8-2. PRE 1 and PRE0 Programming PRE1 and PRE0 PLL, and 8.6.4 PLL VCO Range Select Table 8-3. VPR1 and VPR0 Programming VPR1 and VPR0 Clock Generator Module (CGM) Prescaler Multiplier 8.4.3 PLL Circuits, 8.4.6 . VRS VCO Power-of-Two Range Multiplier MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 121

... PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $0037 Bit LOCK AUTO ACQ ...

Page 122

... Bit Unimplemented $0039 Bit MUL7 MUL6 MUL5 MUL4 PLL.) A value of $0000 in the multiplier select Clock Generator Module (CGM Bit 0 MUL11 MUL10 MUL9 MUL8 Bit 0 MUL3 MUL2 MUL1 MUL0 8.4.3 PLL Circuits and 8.4.6 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 123

... VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $003A Bit VRS7 VRS6 ...

Page 124

... The default divide value recommended for all applications. Technical Data 124 $003B Bit Unimplemented PLL.) RDS[3:0] cannot be written when the 8.4.7 Special Programming Clock Generator Module (CGM Bit 0 RDS3 RDS2 RDS1 RDS0 8.4.3 PLL Circuits and 8.4.6 Exceptions.) Reset MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 125

... PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Technical Data 125 ...

Page 126

... With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Technical Data 126 9.8.3 SIM Break Flag Control Clock Generator Module (CGM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 127

... Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Technical Data 127 ...

Page 128

... Technical Data 128 . This frequency is the input to the phase RDV and the R value programmed in the reference divider. XCLK Circuits, 8.4.6 Programming the Register.) 8.9.3 Choosing a Clock Generator Module (CGM) PLL, and 8.6.5 PLL Filter.) . The DDA MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 129

... PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in a 32.768kHz reference clock (CGMRCLK). applications requiring better stability. applications where stability is not critical. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 8.9.2 Parametric Influences on Reaction Figure 8-10 Figure 8-10 CGMXFC 10 kΩ 0.01 µF 0.033 µF V ...

Page 130

... Clock Generator Module (CGM) Technical Data 130 Clock Generator Module (CGM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 131

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 134 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Clock Start-up from POR or LVI Reset 135 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 136 Reset and System Initialization 136 External Pin Reset ...

Page 132

... SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 152 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 153 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 154 Figure 9-1. Table 9-1 shows the internal signal names used in this section. System Integration Module (SIM summary of the SIM MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 133

... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET ...

Page 134

... IF5 IF4 IF3 IF14 IF13 IF12 IF11 Unimplemented (CGM).) System Integration Module (SIM Bit 0 SBSW Note 0 ILAD 0 LVI IF2 IF1 IF10 IF9 IF8 IF7 IF17 IF16 IF15 Reserved Figure 9-3. This clock can come Section MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 135

... ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor CGMXCLK ICLK SYSTEM INTEGRATION MODULE CGMOUT SIMDIV2 Figure 9-3 ...

Page 136

... An internal reset clears the SIM counter (see external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See Technical Data 136 System Integration Module (SIM) 9.7.2 Stop Mode.) 9.5 SIM Counter), but an 9.8 SIM Registers.) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 137

... SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor shows the relative timing. Table 9-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI ...

Page 138

... Technical Data 138 RST PULLED LOW BY MCU 32 CYCLES Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR Figure 9-6. Sources of Internal Reset System Integration Module (SIM) 32 CYCLES VECTOR HIGH INTERNAL RESET MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 139

... RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V RST pin disables the COP module. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 4096 32 32 CYCLES CYCLES Figure 9-7. POR Recovery 4 – ...

Page 140

... MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. Technical Data 140 voltage falls to the LVI trip falling voltage, V Section 10. Monitor ROM System Integration Module (SIM) . The LVI bit in TRIPF (MON).) When MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 141

... The SIM counter is free-running after all reset states. (See 9.4.2 Active Resets from Internal Sources internal reset recovery sequences.) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor System Integration Module (SIM) System Integration Module (SIM) 9.7.2 Stop Mode for counter control and Technical Data ...

Page 142

... SP – – – – CCR SP – – – CCR – 1[15:8] PC – 1[7:0] System Integration Module (SIM) VECT H VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 143

... The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 9-10.) FROM RESET BREAK I BIT SET? INTERRUPT? NO ...

Page 144

... H register and then restore it prior to exiting the routine. Technical Data 144 CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 9-11 Interrupt Recognition Example System Integration Module (SIM) Figure 9-11 BACKGROUND ROUTINE MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 145

... IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 0 and Bit 1 — Always read 0 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 9-3 summarizes the interrupt sources and the interrupt $FE04 Bit IF6 ...

Page 146

... LVI Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) System Integration Module (SIM) Vector MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 147

... These flags indicate the presence of interrupt requests from the sources shown in 9.6.1.6 Interrupt Status Register 3 Address: Read: Write: Reset: IF17–IF15 — Interrupt Flags 17–15 These flags indicate the presence of an interrupt request from the source shown in MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $FE05 Bit IF14 IF13 IF12 ...

Page 148

... Upon leaving break mode, execution of the second step will clear the flag as normal. Technical Data 148 (BRK).) The SIM puts the CPU into the System Integration Module (SIM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 149

... If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 9-16 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 9-15 shows the timing for wait mode entry. IAB WAIT ADDR WAIT ADDR + 1 IDB ...

Page 150

... IDB $A6 $A6 $A6 $01 Figure 9-16. Wait Recovery from Interrupt or Break 32 CYCLES CYCLES $6E0B $A6 $A6 $A6 Figure 9-17. Wait Recovery from Internal Reset System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 RST VCT H RST VCT L MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 151

... Figure 9-19. Stop Mode Recovery from Interrupt or Break 9.8 SIM Registers The SIM has three memory-mapped registers: • • • MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 9-18 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W instruction ...

Page 152

... Figure 9-20. SIM Break Status Register (SBSR) ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register. System Integration Module (SIM Bit 0 SBSW Note 0 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 153

... PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) LVI — Low-Voltage Inhibit Reset Bit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor $FE01 Bit POR PIN COP ...

Page 154

... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Technical Data 154 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 155

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Security 169 ROM-Resident Routines ...

Page 156

... Resident routines for in-circuit programming and EEPROM emulation 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 156 1 Monitor ROM (MON long as TST , if reset vector is TST , is applied to TST MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 157

... IRQ is held low out of reset, it cannot be used when the reset vector is non-zero because entry into monitor mode in this case requires V MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 10-1 shows an example circuit used to enter monitor on IRQ. TST Monitor ROM (MON) ...

Page 158

... NOTE TST for IRQ voltage level requirements. Monitor ROM (MON) 68HC908LJ12 RST 0.1 µF RESET VECTORS $FFFE $FFFF AND 3) IRQ CGMXFC OSC1 OSC2 REFL DDA V REFH 0.1 µ kΩ PTA0 PTC1 V DD PTA1 PTA2 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 159

... This is to reduce circuit requirements when performing in-circuit programming. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor shows the pin conditions for entering monitor mode. As – The external clock is 4.9152 MHz with PTC1 low or 9.8304 MHz with PTC1 high – IRQ = V ...

Page 160

Table 10-1. Monitor Mode Signal Requirements and Options Address IRQ RST $FFFE/ PTA2 PTA1 PTA0 $FFFF X GND ( TST or V TST ( ...

Page 161

... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the COP is always disabled regardless of the state of IRQ or RST. If monitor mode was entered with V then the COP is disabled as long RST ...

Page 162

... Reset Break Vector Vector Vector High Low High $FFFE $FFFF $FFFC $FEFE $FEFF $FEFC Monitor ROM (MON) NORMAL USER MODE Break SWI SWI Vector Vector Vector Low High Low $FFFD $FFFC $FFFD $FEFD $FEFC $FEFD MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 163

... IRQ, then the internal PLL steps up the external frequency, presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require that the reset vector is blank. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor BIT 0 BIT 1 BIT 2 BIT 3 BIT Figure 10-3. Monitor Data Format ...

Page 164

... Table 10-3. Monitor Baud Rate Selection IRQ PTC1 Frequency V 0 2.4576 MHz TST V 1 2.4576 MHz TST V X 2.4576 MHz 2.4576 MHz SS Monitor ROM (MON) Internal Baud Rate (BPS) 9600 9600 9600 9600 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 165

... Wait 1 bit time before sending next byte. FROM HOST 3 ECHO Notes: A brief description of each monitor mode command is given in Table 10-4 Description Operand Returned MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ADDRESS ADDRESS READ READ HIGH HIGH Figure 10-5. Read Transaction ADDRESS ADDRESS ...

Page 166

... Table 10-6. IREAD (Indexed Read) Command Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA ECHO Monitor ROM (MON) DATA DATA DATA RETURN MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 167

... A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64k-byte memory map. Description Operand Returned MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-7. IWRITE (Indexed Write) Command Write to last address accessed + 1 Single data byte Data None Opcode $19 Command Sequence ...

Page 168

... FROM HOST RUN RUN ECHO HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER Figure 10-7. Stack Pointer at Monitor Mode Entry Monitor ROM (MON MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 169

... PTA0 NOTES Echo delay, 2 bit times Data return delay, 2 bit times Wait 1 bit time before sending next byte. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 4096 + 32 ICLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST FROM MCU Figure 10-8. Monitor Mode Entry Timing ...

Page 170

... FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data 170 Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 171

... During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-10 shows a summary of the ROM-resident Table 10-10. Summary of ROM-Resident Routines Routine Description Program a range of locations ...

Page 172

... MON_LDRNGE, and EE_READ, data is read from FLASH and stored in this array. Technical Data 172 R FILE_PTR $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA ARRAY Monitor ROM (MON DATA 0 DATA DATA 1 BLOCK DATA N MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 173

... FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-11. PRGRNGE Routine PRGRNGE Program a range of locations $FC06 14 bytes ...

Page 174

... Indicates 4x bus frequency DS Data size to be programmed DS FLASH start address DS Reserved data array EQU $FC06 EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LDHX FILE_PTR JSR PRGRNGE Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 175

... The coding example below is to perform a page erase, from $EF00–$EF7F. The Initialization subroutine is the same as the coding example for PRGRNGE (see ERARNGE MAIN: MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-12. ERARNGE Routine ERARNGE Erase a page or the entire array $FCBE 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) ...

Page 176

... LDRNGE Loads data from a range of locations $FF30 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N 10.6.1 PRGRNGE). EQU $FF30 BSR INITIALIZATION : : LDHX FILE_PTR JSR LDRNGE : Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 177

... PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-14. MON_PRGRNGE Routine MON_PRGRNGE Program a range of locations, in monitor mode $FC28 16 bytes ...

Page 178

... Technical Data 178 Table 10-15. MON_ERARNGE Routine MON_ERARNGE Erase a page or the entire array, in monitor mode $FF2C 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Monitor ROM (MON) 10.6.2 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 179

... LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-16. ICP_LDRNGE Routine MON_LDRNGE Loads data from a range of locations, in monitor mode $FF24 11 bytes ...

Page 180

... Table 10-17. EE_WRITE Routine EE_WRITE Emulated EEPROM write. Data size ranges from bytes at a time. $FC00 17 bytes Bus speed (BUS_SPD) (1) Data size (DATASIZE) (2) Starting address (ADDRH) (1) Starting address (ADDRL) Data 1 : Data N Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 181

... MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 10-10). The page control operations PAGE BOUNDARY CONTROL: 8 BYTES DATA ARRAY ...

Page 182

... Indicates 4x bus frequency DS Data size to be programmed DS FLASH starting address DS Reserved data array EQU $FC00 EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LHDX FILE_PTR JSR EE_WRITE Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 183

... RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see EE_READ MAIN: MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Table 10-18. EE_READ Routine EE_READ Emulated EEPROM read. Data size ranges from bytes at a time. $FC03 15 bytes Bus speed (BUS_SPD) ...

Page 184

... FLASH page boundary and the data size 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Technical Data 184 Monitor ROM (MON) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 185

... TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 203 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 204 11.10.5 TIM Channel Registers 207 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 TIM Counter Prescaler ...

Page 186

... Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Technical Data 186 Timer Interface Module (TIM) Figure 11 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 187

... The two TIM channels (per timer) are programmable independently as input capture or output compare channels. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor 11-1. The generic pin names appear in the text that follows. Table 11-1. Pin Name Conventions TIM Generic Pin Names: TIM1 Full TIM ...

Page 188

... CH1F MS1A Figure 11-1. TIM Block Diagram summarizes the timer registers. Timer Interface Module (TIM) TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT LOGIC CH1IE MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

Page 189

... Reset: Read: Timer 1 Channel 0 $0027 Register Low Write: (T1CH0L) Reset: Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Figure 11-2. TIM I/O Register Summary (Sheet MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit ...

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... TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Bit Indeterminate after reset = Unimplemented Timer Interface Module (TIM Bit Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit 8 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Bit Bit ...

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... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Technical Data 192 11.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Figure 11-3 shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Technical Data ...

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... TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE COMPARE Figure 11-3. PWM Period and Pulse Width 11.5.4 Pulse Width Modulation Timer Interface Module (TIM) Register. OVERFLOW OUTPUT OUTPUT COMPARE (PWM). The pulses are MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... I/O pin. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value ...

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... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Table 11-3.) Table 11-3.) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor Registers.) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...

Page 198

... BCFE is at logic 0. After the break, doing the second step clears the status bit. Technical Data 198 9.8.3 SIM Break Flag Control Timer Interface Module (TIM) MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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... MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0, TSC1) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) Timer Interface Module (TIM) Timer Interface Module (TIM) 11 ...

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... Reset clears the TOIE bit TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Technical Data 200 Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Figure 11-4. TIM Status and Control Register (TSC) Timer Interface Module (TIM Bit 0 0 PS2 PS1 PS0 MC68HC908LJ12 Rev. 2.1 — Freescale Semiconductor ...

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