S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet
S9S12XS256J0CAL
Specifications of S9S12XS256J0CAL
Available stocks
Related parts for S9S12XS256J0CAL
S9S12XS256J0CAL Summary of contents
Page 1
MC9S12XS256 Reference Manual Covers MC9S12XS Family MC9S12XS256 MC9S12XS128 MC9S12XS64 HCS12 Microcontrollers MC9S12XS256RMV1 Rev. 1.11 11/2010 freescale.com ...
Page 2
To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ This document contains ...
Page 3
... Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1 .607 Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698 Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712 Appendix E Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735 Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 3 ...
Page 4
... S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 5
... BDM Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.10 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port Integration Module (S12XSPIMV1) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Freescale Semiconductor Chapter 1 Device Overview S12XS Family Chapter 2 S12XS Family Reference Manual, Rev. 1.11 5 ...
Page 6
... Port M Wired-Or Mode Register (WOMM 101 2.3.41 Module Routing Register (MODRR 101 2.3.42 Port P Data Register (PTP 102 2.3.43 Port P Input Register (PTIP 104 2.3.44 Port P Data Direction Register (DDRP 105 2.3.45 Port P Reduced Drive Register (RDRP 106 6 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 7
... Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Memory Mapping Control (S12XMMCV4) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Freescale Semiconductor Chapter 3 S12XS Family Reference Manual, Rev. 1.11 7 ...
Page 8
... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 Chapter 4 Interrupt (S12XINTV2) Chapter 5 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 9
... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Freescale Semiconductor Chapter 6 Chapter 7 Security (S12XS9SECV2) S12XS Family Reference Manual, Rev. 1.11 9 ...
Page 10
... Chapter 9 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 266 Chapter 10 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 11
... Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 11.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 11.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Periodic Interrupt Timer (S12PIT24B4CV1) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Freescale Semiconductor Chapter 11 Chapter 12 S12XS Family Reference Manual, Rev. 1.11 11 ...
Page 12
... PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Serial Communication Interface (S12SCIV5) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 12 Chapter 13 Chapter 14 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 13
... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 15.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 15.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 15.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Freescale Semiconductor Chapter 15 S12XS Family Reference Manual, Rev. 1.11 13 ...
Page 14
... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 492 14 Chapter 16 Timer Module (TIM16B8CV2) Chapter 17 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 15
... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 555 18.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 556 18.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Freescale Semiconductor Chapter 18 S12XS Family Reference Manual, Rev. 1.11 15 ...
Page 16
... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 655 20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 656 20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 16 Chapter 19 Chapter 20 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 17
... A.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 B.1 112-pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 B.2 80-Pin QFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 B.3 64-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 C.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 C.1.1 112-Pin LQFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 Freescale Semiconductor Appendix A Electrical Characteristics Appendix B Package Information Appendix C PCB Layout Guidelines S12XS Family Reference Manual, Rev ...
Page 18
... C.1.3 64-Pin LQFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 D.1 Memory Sizes and Package Options S12XS family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 E.1 Detailed Register Map 713 F.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 18 Appendix D Derivative Differences Appendix E Detailed Register Address Map Appendix F Ordering Information S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 19
... Upward compatible with S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed — Enhanced indexed addressing — Access to large data segments independent of PPAGE Freescale Semiconductor Table D-1 S12XS Family Reference Manual, Rev. 1.11 for memory options and ...
Page 20
... Erase sector size 1024 bytes – Automated program and erase algorithm – Protection scheme to prevent accidental program or erase – Security option to prevent unauthorized access – Sense-amp margin level setting for reads — 4K and 8K byte Data Flash space 20 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 21
... PIT (periodic interrupt timer) — four timers with independent time-out periods — Time-out periods selectable between 1 and 2 Freescale Semiconductor 24 bus clock cycles S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family 21 ...
Page 22
... Hysteresis and configurable pull up/pull down device on all input pins — Configurable drive strength on all output pins • Package Options — 112-pin low-profile quad flat-pack (LQFP) — 80-pin quad flat-pack (QFP) 22 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 23
... This chip family does not support external bus modes. Low-power modes: • System stop modes — Pseudo stop mode — Full stop mode with fast wake-up option • System wait mode Freescale Semiconductor NOTE S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family 23 ...
Page 24
... PWM7 PP7 PM0 RXCAN PM1 TXCAN PM2 PM3 PM4 PM5 PM6 PM7 RXD PS0 PS1 TXD RXD PS2 PS3 TXD PS4 MISO PS5 MOSI SCK PS6 SS PS7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PJ0 PJ1 PJ6 PJ7 Freescale Semiconductor ...
Page 25
... Freescale Semiconductor Table 1-1. Device Register Memory Map Module ) PIM (port integration module MMC (memory map control) PIM (port integration module) Reserved MMC (memory map control) ...
Page 26
... S12XS CPU and BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map. 26 Module Reserved NOTE Table 1-1 is not allocated to any module. S12XS Family Reference Manual, Rev. 1.11 Size (Bytes) 1176 Freescale Semiconductor ...
Page 27
... RAM 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Vectors 0xFFFF Figure 1-2. S12XS Family Global Memory Map Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE DF_HIGH 0x13_FFFF PPAGE 0x3F_FFFF FLASH_LOW 0x7F_FFFF S12XS Family Reference Manual, Rev. 1.11 ...
Page 28
... Mask Set Number Part ID 0M05M $C0C0 0M04M $C1C0 1M04M $C1C1 0M04M $C1C0 1M04M $C1C1 S12XS Family Reference Manual, Rev. 1.11 SIZE/ SIZE/ DF_HIGH 2 EPAGE 0x10_1FFF 0x10_1FFF 0x10_0FFF Table 1-3 shows the assigned part ID 1 Version ID 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Freescale Semiconductor 3 ...
Page 29
... The XS family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. The S12XS family devices are offered in the following package options: • 112-pin LQFP • 80-pin QFP • 64-pin LQFP Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family 29 ...
Page 30
... Pins shown in BOLD are not available on the 80 QFP package S12XS Family Reference Manual, Rev. 1.11 84 VRH 83 VDDA 82 PAD15/AN15 81 PAD07/AN07 80 PAD14/AN14 79 PAD06/AN06 78 PAD13/AN13 77 PAD05/AN05 76 PAD12/AN12 75 PAD04/AN04 74 PAD11/AN11 73 PAD03/AN03 72 PAD10/AN10 71 PAD02/AN02 70 PAD09/AN09 69 PAD01/AN01 68 PAD08/AN08 67 PAD00/AN00 66 VSS2 65 VDD 64 PA7 63 PA6 62 PA5 61 PA4 60 PA3 59 PA2 58 PA1 57 PA0 Freescale Semiconductor ...
Page 31
... PWM3/KWP3/PP3 TXD1/IOC2/PWM2/KWP2/PP2 IOC1/PWM1/KWP1/PP1 RXD1/IOC0/PWM0/KWP0/PP0 PWM4/IOC4/PT4 VREG_API/PWM5/IOC5/PT5 PWM6/IOC6/PT6 PWM7/IOC7/PT7 MODC/BKGD Figure 1-4. S12XS Family Pin Assignments 80-pin QFP Package Freescale Semiconductor S12XS Family 4 IOC0/PT0 5 80QFP IOC1/PT1 6 7 IOC2/PT2 8 IOC3/PT3 VDDF 9 VSS1 Pins shown in BOLD are 14 not available on the 64 15 QFP package PB0 ...
Page 32
... VREG_API/PWM5/IOC5/PT5 PWM6/IOC6/PT6 PWM7/IOC7/PT7 MODC/BKGD Figure 1-5. S12XS Family Pin Assignments 64-pin LQFP Package S12XS Family 4 64LQFP PB0 16 S12XS Family Reference Manual, Rev. 1.11 48 VRH 47 VDDA 46 PAD07/AN07 45 PAD06/AN06 44 PAD05/AN05 43 PAD04/AN04 42 PAD03/AN03 41 PAD02/AN02 40 PAD01/AN01 39 PAD00/AN00 38 VSS2 37 VDD PA3 36 PA2 35 PA1 34 PA0 33 Freescale Semiconductor ...
Page 33
... Port E pins inc. IRQ/XIRQ input only Port H Port J Port K Port M Port P Port S Port T Sum of Ports I/O Power Pairs VDDX/VSSX Table 1-5. Peripheral - Port Routing Options “X” denotes reset condition, “O” denotes a possible rerouting 1 under software control Freescale Semiconductor 1-5. 112 LQFP 16/ ...
Page 34
Table 1-6 provides a pin out summary listing the availability and functionality of individual pins for each package option. Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PP3 KWP3 PP2 KWP2 ...
Page 35
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PT5 IOC5 PT6 IOC6 PT7 IOC7 PK5 — PK4 — PJ1 ...
Page 36
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PE7 XCLKS PE6 — PE5 — PE4 ECLK VSSX2 — VDDX2 ...
Page 37
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PE1 IRQ PE0 XIRQ PA0 — PA1 — PA2 — PA3 ...
Page 38
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PAD10 AN10 PAD03 AN03 PAD11 AN11 PAD04 AN04 PAD12 AN12 PAD05 ...
Page 39
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func PM7 — PM6 — PS0 RXD0 PS1 TXD0 PS2 RXD1 PS3 ...
Page 40
Package Terminal LQFP QFP LQFP 2nd Pin 112 80 64 Func. 106 76 61 VSSX1 — 107 77 62 VDDX1 — 108 - - PK7 — 109 78 63 PP7 KWP7 110 - - PP6 KWP6 111 79 64 PP5 ...
Page 41
... ATD0. 1.2.3.6 PA[7:0] — Port A I/O Pins PA[7:0] are general-purpose input or output pins. 1.2.3.7 PB[7:0] — Port B I/O Pins PB[7:0] are general-purpose input or output pins. Freescale Semiconductor NOTE NOTE in all applications. SS S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family ...
Page 42
... PJ[1:0] / KWJ[1:0] — PORT J I/O Pins 1-0 PJ[1:0] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs. 1.2.3.17 PK[7,5:0] — Port K I/O Pins 7 and 5-0 PK[7,5:0] are a general-purpose input or output pins. 42 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 43
... PP[6:3] / KWP[6:3] / PWM[6:3] — Port P I/O Pins 6-3 PP[6:3] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs. They can be configured as pulse width modulator (PWM) channel 6-3 output. Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family ...
Page 44
... PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 1 (SCI1). 1.2.3.35 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 1 (SCI1). 44 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 45
... All V DDX 1.2.4.2 VDDR — Power Pin for Internal Voltage Regulator Power supply input to the internal voltage regulator. Freescale Semiconductor NOTE SSX S12XS Family Reference Manual, Rev. 1.11 Device Overview S12XS Family pins are connected together internally. ...
Page 46
... V Reference voltages for the analog-to-digital converter. 5.0 V 1.8 V Internal power and ground generated by internal regulator for the internal core 2.8 V Internal power and ground generated by internal regulator for the internal NVM. S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 47
... VDDPLL VSSPLL 47 Nominal Description Voltage 1.8 V Provides operating voltage and ground for the phased-locked loop. This allows the 0 V supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 48
... The on-chip phase locked loop (PLL) • the PLL self clocking • the oscillator 48 shows the clock connections from the CRG to all modules. NOTE CAN0 ATD0 Oscillator Clock S12X Figure 1-6. Clock Connections S12XS Family Reference Manual, Rev. 1.11 PIT TIM PIM PWM FLASH Freescale Semiconductor ...
Page 49
... This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory. Freescale Semiconductor 1-6, these system clocks are used throughout the MCU to drive the core, 1.4.2 Power Modes ...
Page 50
... The internal CPU clock is switched off. All peripherals can be active in system wait mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked ends system wait mode. 50 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 51
... Vectors Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module (S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each Freescale Semiconductor NOTE CCR Reset Source Mask Power-On Reset (POR) ...
Page 52
... Yes (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) Yes PIEJ (PIEJ7-PIEJ0) Yes PIEH (PIEH7-PIEH0) Yes CRGINT(LOCKIE) Refer to CRG interrupt section CRGINT (SCMIE) Refer to CRG interrupt section Freescale Semiconductor WAIT Wake up — — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
Page 53
... Effects of Reset When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash configuration registers. Freescale Semiconductor CCR Mask I bit FLASH I bit ...
Page 54
... Table 1-11. Initial COP Rate Configuration NV[2:0] in CR[2:0] in COPCTL Register 000 001 010 011 100 101 110 111 Table 1-12. Initial WCOP Configuration NV[3] in WCOP in COPCTL Register 1 0 S12XS Family Reference Manual, Rev. 1.11 111 110 101 100 011 010 001 000 0 1 Freescale Semiconductor ...
Page 55
... The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17]. Freescale Semiconductor Table 1-13. ATD0 External Trigger Sources Connectivity ...
Page 56
... The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode 56 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 57
... The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above described reset cases. Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1) EXTAL MCU XTAL Figure 1-8. Full Swing Pierce Oscillator Connections (XCLKS = 0) Figure 1-9. External Clock Connections (XCLKS = 0) Freescale Semiconductor EXTAL C 1 MCU Crystal or Ceramic Resonator XTAL ...
Page 58
... Device Overview S12XS Family 58 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 59
... Port AD associated with one 16-channel ATD module Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and select pull-up or pull-down devices. Freescale Semiconductor Description of Changes • Corrected reduced drive strength to 1/5 • Separated PE1,0 bit descriptions from other PE GPIO • ...
Page 60
... This section lists and describes the signals that connect off-chip. Table shows all the pins and their functions that are controlled by the Port Integration Module. Refer to the device definition for the availability of the individual pins in the different package options. 60 NOTE S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 61
... PE[3:2] GPIO PE[1] IRQ GPI PE[0] XIRQ GPI K PK[7,5:0] GPIO Freescale Semiconductor NOTE Table 2-1. Pin Functions and Priorities I/O Description I MODC input during RESET I/O S12X_BDM communication pin I/O General purpose I/O General purpose I External clock selection input during RESET ...
Page 62
... I/O General purpose I Serial Communication Interface 1 receive pin I/O General purpose O Serial Communication Interface 0 transmit pin I/O General purpose I Serial Communication Interface 0 receive pin I/O General purpose S12XS Family Reference Manual, Rev. 1.11 Pin Function after Reset GPIO GPIO Freescale Semiconductor ...
Page 63
... PM1 TXCAN0 (TXD1) GPIO PM0 RXCAN0 (RXD1) GPIO Freescale Semiconductor I/O Description I/O General purpose I/O Serial Peripheral Interface 0 serial clock pin I/O General purpose I/O Serial Peripheral Interface 0 master out/slave in pin I/O General purpose I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode ...
Page 64
... I/O General purpose; with interrupt I/O General purpose; with interrupt I/O General purpose; with interrupt I/O General purpose; with interrupt I/O General purpose I ATD analog S12XS Family Reference Manual, Rev. 1.11 Pin Function after Reset GPIO GPIO GPIO GPIO Freescale Semiconductor ...
Page 65
... Non-PIM address range : 0x0031 K 0x0032 PORTK—Port K Data Register 0x0033 DDRK—Port K Data Direction Register 0x0034 Non-PIM address range : 0x023F Freescale Semiconductor Table 2-2. Block Memory Map Register S12XS Family Reference Manual, Rev. 1.11 Port Integration Module (S12XSPIMV1) Access Reset Value Section/Page R/W 0x00 2 ...
Page 66
... R/W 0x00 2.3.37/2-99 R/W 0x00 2.3.38/2-100 R/W 0x00 2.3.39/2-100 R/W 0x00 2.3.40/2-101 R/W 0x00 2.3.41/2-101 R/W 0x00 2.3.42/2-102 4 R 2.3.43/2-104 R/W 0x00 2.3.44/2-105 R/W 0x00 2.3.45/2-106 R/W 0x00 2.3.46/2-106 R/W 0x00 2.3.47/2-107 R/W 0x00 2.3.48/2-107 R/W 0x00 2.3.49/2-108 Freescale Semiconductor ...
Page 67
... Write access not applicable for one or more register bits. Refer to register description. 2 Refer to memory map in SoC Guide to determine related module. 3 Mode dependent. 4 Read always returns logic level on pins. Freescale Semiconductor Table 2-2. Block Memory Map (continued) Register S12XS Family Reference Manual, Rev. 1.11 Port Integration Module (S12XSPIMV1) Access Reset Value Section/Page ...
Page 68
... DDRE4 DDRE3 Non-PIM Address Range 0 0 PUPEE 0 0 RDPE Non-PIM Address Range S12XS Family Reference Manual, Rev. 1. Bit 0 PA2 PA1 PA0 PB2 PB1 PB0 DDRA2 DDRA1 DDRA0 DDRB2 DDRB1 DDRB0 PE1 PE0 PE2 0 0 DDRE2 0 PUPBE PUPAE 0 RDPB RDPA Freescale Semiconductor ...
Page 69
... PTIT6 PTIT W 0x0242 R DDRT7 DDRT6 DDRT W 0x0243 R RDRT7 RDRT6 RDRT W 0x0244 R PERT7 PERT6 PERT W 0x0245 R PPST7 PPST6 PPST W = Unimplemented or Reserved Freescale Semiconductor DIV16 EDIV4 EDIV3 Non-PIM Address Range PK5 PK4 PK3 DDRK5 DDRK4 DDRK3 Non-PIM Address Range PTT5 PTT4 PTT3 PTIT5 ...
Page 70
... PTS2 PTS1 PTS0 PTIS2 PTIS1 PTIS0 DDRS2 DDRS1 DDRS0 RDRS2 RDRS1 RDRS0 PERS2 PERS1 PERS0 PPSS2 PPSS1 PPSS0 WOMS2 WOMS1 WOMS0 PTM2 PTM1 PTM0 PTIM2 PTIM1 PTIM0 DDRM2 DDRM1 DDRM0 RDRM2 RDRM1 RDRM0 PERM2 PERM1 PERM0 PPSM2 PPSM1 PPSM0 Freescale Semiconductor ...
Page 71
... R PTIH7 PTIH6 PTIH W 0x0262 R DDRH7 DDRH6 DDRH W 0x0263 R RDRH7 RDRH6 RDRH W 0x0264 R PERH7 PERH6 PERH W = Unimplemented or Reserved Freescale Semiconductor WOMM5 WOMM4 WOMM3 0 0 MODRR4 PTP5 PTP4 PTP3 PTIP5 PTIP4 PTIP3 DDRP5 DDRP4 DDRP3 RDRP5 RDRP4 RDRP3 PERP5 PERP4 PERP3 PPSP5 ...
Page 72
... PT1AD04 PT1AD03 S12XS Family Reference Manual, Rev. 1. Bit 0 PPSH2 PPSH1 PPSH0 PIEH2 PIEH1 PIEH0 PIFH2 PIFH1 PIFH0 0 PTJ1 PTJ0 0 PTIJ1 PTIJ0 0 DDRJ1 DDRJ0 0 RDRJ1 RDRJ0 0 PERJ1 PERJ0 0 PPSJ1 PPSJ0 0 PIEJ1 PIEJ0 0 PIFJ1 PIFJ0 PT0AD02 PT0AD01 PT0AD00 PT1AD02 PT1AD01 PT1AD00 Freescale Semiconductor ...
Page 73
... The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt enabled. 2. Select either a pull-up or pull-down device active. Freescale Semiconductor PER0AD05 ...
Page 74
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling edge Disabled Rising edge Pull Up Falling edge Pull Down Rising edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling edge Disabled Rising edge Disabled Falling edge Disabled Rising edge Freescale Semiconductor ...
Page 75
... The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin. If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. Freescale Semiconductor ...
Page 76
... Table 2-6. DDRA Register Field Descriptions Description 5 4 DDRB5 DDRB4 DDRB3 0 0 Table 2-7. DDRB Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write DDRA2 DDRA1 Access: User read/write DDRB2 DDRB1 Freescale Semiconductor 1 0 DDRA0 DDRB0 0 ...
Page 77
... Reset Unimplemented or Reserved 1 Read: Anytime. The data source depends on the data direction value. Write: Anytime. 2 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Freescale Semiconductor Figure 2-5. PIM Reserved Registers ...
Page 78
... R DDRE7 DDRE6 W Reset Unimplemented or Reserved Figure 2-7. Port E Data Direction Register (DDRE) 1 Read: Anytime. The data source depends on the data direction value. Write: Anytime. 78 Description DDRE5 DDRE4 DDRE3 S12XS Family Reference Manual, Rev. 1.11 Access: User read/write DDRE2 Freescale Semiconductor 1 ...
Page 79
... This bit configures whether a pull-up device is activated on all associated port input pins pin is used as output this bit has no effect. Pins 5 and 6 have pull-down devices enabled only during reset. This bit has no effect on these pins. 1 Pull-up device enabled 0 Pull-up device disabled Freescale Semiconductor Table 2-9. DDRE Register Field Descriptions Description 5 4 ...
Page 80
... The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled 80 Description RDPE Description S12XS Family Reference Manual, Rev. 1.11 1 Access: User read/write RDPB RDPA Freescale Semiconductor ...
Page 81
... W Mode Reset: Depen- 1 dent Special 0 1 single-chip Normal 1 1 single-chip = Unimplemented or Reserved Figure 2-10. ECLK Control Register (ECLKCTL) 1 Read: Anytime. Write: Anytime. Freescale Semiconductor Description DIV16 EDIV4 EDIV3 S12XS Family Reference Manual, Rev. 1.11 Port Integration Module (S12XSPIMV1) Access: User read/write ...
Page 82
... ECLK rate = bus clock rate divided by 32 2.3.13 PIM Reserved Register Address 0x001D (PRR Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented 82 Description Figure 2-11. PIM Reserved Register S12XS Family Reference Manual, Rev. 1.11 1 Access: User read Freescale Semiconductor ...
Page 83
... This register is reserved for factory testing of the PIM module and is not available in normal operation. Writing to this register when in special modes can alter the pin functionality. Address 0x001F Reset Unimplemented or Reserved 1. Implementation pim_xe.01.01 and later Freescale Semiconductor Figure 2-12. IRQ Control Register (IRQCR) Description 1 5 ...
Page 84
... Read: Anytime. The data source depends on the data direction value. Write: Anytime PK5 PK4 PK3 Figure 2-14. Port K Data Register (PORTK) Description DDRK5 DDRK4 DDRK3 S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PK2 PK1 PK0 Access: User read/write DDRK2 DDRK1 DDRK0 Freescale Semiconductor 1 1 ...
Page 85
... The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the related channel is enabled. • The routed PWM function takes precedence over the general purpose I/O function if the related channel is enabled. Freescale Semiconductor Description 5 4 ...
Page 86
... A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 86 Description 5 4 PTIT5 PTIT4 PTIT3 Unaffected by reset Figure 2-17. Port T Input Register (PTIT) Table 2-17. PTIT Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read PTIT2 PTIT1 Freescale Semiconductor 1 0 PTIT0 u ...
Page 87
... Associated pin configured as input 2.3.21 Port T Reduced Drive Register (RDRT) Address 0x0243 RDRT7 RDRT6 W Reset 0 0 Figure 2-19. Port T Reduced Drive Register (RDRT) Freescale Semiconductor 5 4 DDRT5 DDRT4 DDRT3 0 0 Table 2-18. DDRT Register Field Descriptions Description 5 4 RDRT5 RDRT4 ...
Page 88
... Table 2-19. RDRT Register Field Descriptions Description 5 4 PERT5 PERT4 PERT3 0 0 Table 2-20. PERT Register Field Descriptions Description 5 4 PPST5 PPST4 PPST3 0 0 S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PERT2 PERT1 Access: User read/write PPST2 PPST1 Freescale Semiconductor 1 0 PERT0 PPST0 0 ...
Page 89
... PTTRR6 W Routing PWM7 PWM6 Option Reset Unimplemented or Reserved 1 Read: Anytime. Write: Anytime. This register configures the re-routing of PWM and TIM channels on alternative pins. Freescale Semiconductor Table 2-21. PPST Register Field Descriptions Description Figure 2-22. PIM Reserved Register 5 4 PTTRR5 PTTRR4 PWM5 ...
Page 90
... This register controls the routing of TIM channel 1. 1 IOC1 routed to PP1 0 IOC1 routed to PT1 0 Port T peripheral routing— PTTRR This register controls the routing of TIM channel 0. 1 IOC0 routed to PP0 0 IOC0 routed to PT0 90 Description S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 91
... If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. • The SPI0 function takes precedence over the general purpose I/O function if enabled. Freescale Semiconductor 5 4 PTS5 ...
Page 92
... Address 0x0249 PTIS7 PTIS6 W Reset Unimplemented or Reserved 1 Read: Anytime. Write:Never, writes to this register have no effect. 92 Description PTIS5 PTIS4 PTIS3 Unaffected by reset Figure 2-25. Port S Input Register (PTIS) S12XS Family Reference Manual, Rev. 1.11 Access: User read PTIS2 PTIS1 PTIS0 Freescale Semiconductor 1 ...
Page 93
... Depending on the configuration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the data direction bit will not change. 1 Associated pin configured as output 0 Associated pin configured as input Freescale Semiconductor Table 2-24. PTIS Register Field Descriptions Description 5 ...
Page 94
... Pull device disabled RDRS5 RDRS4 RDRS3 0 0 Description 5 4 PERS5 PERS4 PERS3 1 1 Table 2-27. PERS Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write RDRS2 RDRS1 Access: User read/write PERS2 PERS1 Freescale Semiconductor 1 0 RDRS0 PERS0 1 ...
Page 95
... In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no influence on pins used as input. 1 Output buffer operates as open-drain output. 0 Output buffer operates as push-pull output. Freescale Semiconductor 5 4 PPSS5 ...
Page 96
... Figure 2-32. Port M Data Register (PTM) Table 2-30. PTM Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read Access: User read/write PTM2 PTM1 (MISO0) TXCAN0 — — (TXD1 Freescale Semiconductor PTM0 RXCAN0 (RXD1) 0 ...
Page 97
... The CAN0 function takes precedence over the general purpose I/O function if enabled. • The SCI1 function takes precedence over the general purpose I/O function if enabled. Freescale Semiconductor Description S12XS Family Reference Manual, Rev. 1.11 Port Integration Module (S12XSPIMV1) ...
Page 98
... Unaffected by reset Figure 2-33. Port M Input Register (PTIM) Table 2-31. PTIM Register Field Descriptions Description 5 4 DDRM5 DDRM4 DDRM3 0 0 S12XS Family Reference Manual, Rev. 1.11 Access: User read PTIM2 PTIM1 Access: User read/write DDRM2 DDRM1 Freescale Semiconductor 1 0 PTIM0 DDRM0 0 ...
Page 99
... This bit configures the drive strength of the associated output pin as either full or reduced pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled Freescale Semiconductor Description 5 4 ...
Page 100
... If CAN0 is active the selection of a pull-down device on the RXCAN input will have no effect pull-down device selected 0 A pull-up device selected 100 PERM5 PERM4 PERM3 Description PPSM5 PPSM4 PPSM3 Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PERM2 PERM1 PERM0 Access: User read/write PPSM2 PPSM1 PPSM0 Freescale Semiconductor 1 1 ...
Page 101
... R MODRR7 MODRR6 W Routing SCI1 SCI1 Option Reset Unimplemented or Reserved Figure 2-39. Module Routing Register (MODRR) 1 Read: Anytime. Write: Anytime. This register configures the re-routing of SCI1 and SPI0 on alternative ports. MODRRx 7 Freescale Semiconductor WOMM5 WOMM4 WOMM3 Description MODRR4 — SPI0 — ...
Page 102
... Figure 2-40. Port P Data Register (PTP) S12XS Family Reference Manual, Rev. 1.11 PS2 PP0 PM0 1 Reserved SS0 PS7 PM3 Access: User read/write PTP2 PTP1 PWM2 PWM1 — (IOC2) (IOC1) — (TXD1) — Freescale Semiconductor 1 0 PTP0 PWM0 (IOC0) (RXD1) 0 ...
Page 103
... The TIM function takes precedence over SCI1 and the general purpose I/O function if the related channel is enabled. • The SCI1 function takes precedence over the general purpose I/O function if enabled. • Pin interrupts can be generated if enabled in input or output mode. Freescale Semiconductor Table 2-39. PTP Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 ...
Page 104
... A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 104 Description 5 4 PTIP5 PTIP4 PTIP3 Unaffected by reset Figure 2-41. Port P Input Register (PTIP) Table 2-40. PTIP Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read PTIP2 PTIP1 Freescale Semiconductor 1 0 PTIP0 u ...
Page 105
... The PWM forces the I/O state output for an enabled channel. Else the TIM forces the I/O state output for a timer port associated with an enabled output compare. In this case the data direction bit will not change. 1 Associated pin configured as output 0 Associated pin configured as input Freescale Semiconductor ...
Page 106
... Pull device disabled 106 5 4 RDRP5 RDRP4 RDRP3 0 0 Description 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-43. PERP Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write RDRP2 RDRP1 Access: User read/write PPSP2 PPSP1 Freescale Semiconductor 1 0 RDRP0 PPSP0 0 ...
Page 107
... Write: Anytime. Field 7-0 Port P interrupt enable— PIEP This bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 Interrupt enabled 0 Interrupt disabled (interrupt flag masked) Freescale Semiconductor 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-44. PPSP Register Field Descriptions ...
Page 108
... Table 2-46. PIFP Register Field Descriptions Description 5 4 PTH5 PTH4 PTH3 0 0 Figure 2-48. Port H Data Register (PTH) Table 2-47. PTH Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PIFP2 PIFP1 Access: User read/write PTH2 PTH1 Freescale Semiconductor 1 0 PIFP0 PTH0 0 ...
Page 109
... Table 2-49. DDRH Register Field Descriptions Field 7-0 Port H data direction— DDRH This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input Freescale Semiconductor 5 4 PTIH5 PTIH4 PTIH3 Unaffected by reset Figure 2-49 ...
Page 110
... Pull device disabled 110 5 4 RDRH5 RDRH4 RDRH3 0 0 Description 5 4 PERH5 PERH4 PERH3 0 0 Table 2-51. PERH Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write RDRH2 RDRH1 Access: User read/write PERH2 PERH1 Freescale Semiconductor 1 0 RDRH0 PERH0 0 ...
Page 111
... Write: Anytime. Field 7-0 Port H interrupt enable— PIEH This bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 Interrupt enabled 0 Interrupt disabled (interrupt flag masked) Freescale Semiconductor 5 4 PPSH5 PPSH4 PPSH3 0 0 Table 2-52. PPSH Register Field Descriptions ...
Page 112
... Table 2-54. PIFH Register Field Descriptions Description Figure 2-56. Port J Data Register (PTJ) Table 2-55. PTJ Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PIFH2 PIFH1 Access: User read/write PTJ1 Freescale Semiconductor 1 0 PIFH0 PTJ0 0 ...
Page 113
... Read: Anytime. Write: Anytime. Field 7-6, 1-0 Port J data direction— DDRJ This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input Freescale Semiconductor Unaffected by reset Figure 2-57. Port J Input Register (PTIJ) Table 2-56 ...
Page 114
... The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled 114 Table 2-58. RDRJ Register Field Descriptions Description Table 2-59. PERJ Register Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write RDRJ1 Access: User read/write PERJ1 Freescale Semiconductor 1 0 RDRJ0 PERJ0 1 ...
Page 115
... Figure 2-62. Port J Interrupt Enable Register (PIEJ) 1 Read: Anytime. Write: Anytime. Field 7-6, 1-0 Port J interrupt enable— PIEJ This bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 Interrupt enabled 0 Interrupt disabled (interrupt flag masked) Freescale Semiconductor Table 2-60. PPSJ Register Field Descriptions Description 5 4 ...
Page 116
... Table 2-62. PIFJ Register Field Descriptions Description 5 4 PT0AD05 PT0AD04 PT0AD03 AN13 AN12 AN11 0 0 Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PIFJ1 Access: User read/write PT0AD02 PT0AD01 AN10 AN9 Freescale Semiconductor 1 0 PIFJ0 PT0AD00 AN8 0 ...
Page 117
... This bit determines whether the associated pin is an input or output. To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”. 1 Associated pin configured as output 0 Associated pin configured as input Freescale Semiconductor ...
Page 118
... Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled 118 DDR1AD05 DDR1AD04 DDR1AD03 Description RDR0AD05 RDR0AD04 RDR0AD03 Description S12XS Family Reference Manual, Rev. 1.11 Access: User read/write DDR1AD02 DDR1AD01 DDR1AD00 Access: User read/write RDR0AD02 RDR0AD01 RDR0AD00 Freescale Semiconductor 1 1 ...
Page 119
... Port AD0 pull device enable—Enable pull-up device on input pin PER0AD0 This bit controls whether a pull device on the associated port input pin is active pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled Freescale Semiconductor RDR1AD05 RDR1AD04 ...
Page 120
... Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output or input of a peripheral module. 120 PER1AD05 PER1AD04 PER1AD03 Description Unaffected by reset Figure 2-72. PIM Reserved Registers S12XS Family Reference Manual, Rev. 1.11 Access: User read/write PER1AD02 PER1AD01 PER1AD00 Access: User read Freescale Semiconductor 1 1 ...
Page 121
... If a peripheral module controls the pin the contents of the data direction register is ignored Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address (2.4.2.1/2-121). Freescale Semiconductor Table 2-71. Register availability per port Reduced ...
Page 122
... This register selects either a pull-up or pull-down device if enabled. It only becomes active if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-or output. 122 NOTE PTI DDR 0 1 data out output enable module enable S12XS Family Reference Manual, Rev. 1.11 PIN Freescale Semiconductor ...
Page 123
... Port E pin PE[ used for either general-purpose I the free-running clock ECLKX2 output running at the core clock rate. Port E pin PE[ used for either general-purpose I the free-running clock ECLK output running at the bus clock rate or at the programmed divided clock rate. Freescale Semiconductor NOTE S12XS Family Reference Manual, Rev. 1.11 Port Integration Module (S12XSPIMV1) ...
Page 124
... Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN0 or with the SCI1 subsystem. Port M pins PM[5:2] can be used for general purpose I/O. 2.4.3.8 Port P This port is associated with the PWM, TIM and SCI1. 124 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 125
... The minimum time varies over process conditions, temperature and voltage Table 2-72). Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set Figure 2-74. Interrupt Glitch Filter on Port P, H and J (PPS=0) Freescale Semiconductor (Figure 2-75) shorter than a specified time from generating an uncertain t pign ...
Page 126
... Mode STOP Unit ≤ bus clocks pulse 3 < t < 4 bus clocks pulse ≥ bus clocks pulse t pulse Figure 2-75. Pulse Illustration S12XS Family Reference Manual, Rev. 1.11 1 STOP ≤ pulse pign t < t < t pign pulse pval ≥ pulse pval Freescale Semiconductor ...
Page 127
... The MMC module controls the multi-master priority accesses, the selection of internal resources . Internal buses, including internal memories and peripherals, are controlled in this module. The local address space for each master is translated to a global memory space. Freescale Semiconductor Sections Affected - Minor changes ...
Page 128
... Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes Resources are also called targets. 1. 128 Table 3-1. Acronyms and Abbreviations 1 (internal, and peripherals) (see S12XS Family Reference Manual, Rev. 1.11 Figure 3-1 ) Freescale Semiconductor ...
Page 129
... MMC is inactive during stop mode. 3.1.4.2 Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used. 3.1.5 Block Diagram Figure 3-1 shows a block diagram of the MMC. Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Memory Mapping Control (S12XMMCV4) 129 ...
Page 130
... Table 3-2. External Input Signals Associated with the MMC Signal I/O MODC I 130 Address Decoder & Priority Target Bus Controller PGMFLASH RAM Figure 3-1. MMC Block Diagram Description Mode input S12XS Family Reference Manual, Rev. 1.11 CPU DBG Peripherals Availability Latched after RESET (active low) Freescale Semiconductor ...
Page 131
... DP15 W 0x0012 Reserved 0x0013 MMCCTL1 R MGRAMON W 0x0014 Reserved 0x0015 PPAGE R PIX7 W 0x0016 RPAGE R RP7 W 0x0017 EPAGE R EP7 W 3.3.2 Register Descriptions Freescale Semiconductor GP6 GP5 GP4 DP14 DP13 DP12 DFIFRON PGMIFRON PIX6 PIX5 PIX4 RP6 RP5 RP4 EP6 EP5 EP4 = Unimplemented or Reserved Figure 3-2 ...
Page 132
... Figure 3-5. Mode Transition Diagram when MCU is Unsecured 132 Figure 3-3. Mode Register (MODE) Figure Table 3-3. MODE Field Descriptions Description Figure 3-4. 1 S12XS Family Reference Manual, Rev. 1. 3-5). Figure 3-3). Figure 3-5 illustrates all allowed mode Special 0 Single-Chip RESET (SS) 0 Freescale Semiconductor ...
Page 133
... Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64KB pages GP[6:0] accessed. Example 3-1. This example demonstrates usage of the GPAGE register LDX #0x5000 MOVB #0x14, GPAGE GLDAA X Freescale Semiconductor GP5 GP4 GP3 Global Address [22:0] ...
Page 134
... Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are “direct page aware” and can ;automatically select direct mode. S12XS Family Reference Manual, Rev. 1. DP10 DP9 0 0 Figure 3-9). Bit0 Bit7 Freescale Semiconductor 0 DP8 0 ...
Page 135
... Not visible in the global memory map. 1 Visible in the global memory map. 3.3.2.5 Program Page Index Register (PPAGE) Address: 0x0015 PIX7 PIX6 W Reset 1 1 Figure 3-11. Program Page Index Register (PPAGE) Read: Anytime Freescale Semiconductor DFIFRON PGMIFRON Table 3-6. MMCCTL1 Field Descriptions Description PIX5 ...
Page 136
... Address: CPU Local Address Figure 3-12. PPAGE Address Mapping NOTE Table 3-7. PPAGE Field Descriptions Description RP5 RP4 RP3 S12XS Family Reference Manual, Rev. 1.11 Figure 3-12). This supports Bit0 Address [13:0] or BDM Local Address 2 1 RP2 RP1 1 0 Freescale Semiconductor 0 RP0 1 ...
Page 137
... The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF). The page 0xFD (reset value) contains unimplemented area in the range not occupied by RAM if RAMSIZE is less than 12KB (Refer to “Implemented Memory Freescale Semiconductor Global Address [22:0] Bit19 Bit18 Bit12 ...
Page 138
... Memory Mapping Control (S12XMMCV4) The two fixed 4KB pages (0xFE, 0xFF) contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB (Refer to Section 3.4.2.3, “Implemented Memory 138 Map). S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 139
... Data FLASH addresses in the Local map format Field 7–0 Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH EP[7:0] array pages accessed in the Data FLASH Page Window. Freescale Semiconductor EP5 EP4 EP3 ...
Page 140
... Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0xFF. 140 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 141
... RAM window 0x2000 8KB RAM 0x4000 Unpaged 16KB FLASH 0x8000 16KB FLASH window 0xC000 Unpaged 16KB FLASH Reset Vectors 0xFFFF Figure 3-17. Expansion of the Local Address Map Freescale Semiconductor 0x00_0000 0x00_0800 0x00_1000 0x0F_E000 EPAGE 0x10_0000 RPAGE 0x13_FC00 0x14_0000 PPAGE 0x40_0000 0x7F_4000 0x7F_8000 ...
Page 142
... EPAGE allows accessing up to 256KB of Data Flash in the system by using the eight EPAGE index bits to page 1KB blocks into the Data FLASH page window located in the local CPU memory space from address 0x0800 to address 0x0BFF. 142 Instructions). S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 143
... The generated global address is a result of concatenation of the BDM local address with the BDMGPR register [22:16] in the case of a hardware command or concatenation of the CPU local address and the BDMGPR register [22:16] in the case of a firmware command (see Freescale Semiconductor Figure S12XS Family Reference Manual, Rev. 1.11 Memory Mapping Control (S12XMMCV4) Section 3 ...
Page 144
... BDM FIRMWARE COMMAND Global Address [22:0] Bit16 Bit15 Figure 3-18. BDMGPR Address Mapping $Address RAM_LOW = 0x10_0000 minus RAMSIZE DF_HIGH = 0x10_0000 plus DFLASHSIZE FLASH_LOW = 0x80_0000 minus FLASHSIZE S12XS Family Reference Manual, Rev. 1.11 Bit0 BDM Local Address Bit0 CPU Local Address Figure 3- Freescale Semiconductor ...
Page 145
... Misaligned word access to the last location of any global page (64KB) by any global instruction, is performed by accessing the last byte of the page and the first byte of the same page, considering the above mentioned misaligned access cases. Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Memory Mapping Control (S12XMMCV4) ...
Page 146
... Figure 3-19. S12X CPU & BDM Global Address Mapping 146 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE DF_HIGH RPAGE 0x13_FFFF PPAGE 0x3F_FFFF FLASH_LOW 0x7F_FFFF S12XS Family Reference Manual, Rev. 1.11 Global Memory Map 2K REGISTERS Unimplemented RAM RAM Data FLASH Data FLASH Resources Unimplemented Space Unimplemented FLASH FLASH Freescale Semiconductor ...
Page 147
... In addition the MMC handles all CPU read data bus swapping operations. All internal resources are connected to specific target buses (see BDM S12X1 MMC Data FLASH Freescale Semiconductor Address Decoder & Priority Target Bus Controller XBUS0 PGMFLASH RAM Figure 3-20 ...
Page 148
... The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL instruction. 148 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 149
... RTC instruction must be called using the CALL instruction even when the correct page is already present in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Memory Mapping Control (S12XMMCV4) ...
Page 150
... Memory Mapping Control (S12XMMCV4) 150 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 151
... XGATE module can be nested one level deep. The HPRIO register and functionality of the original S12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. Freescale Semiconductor Table 4-1. Revision History Description of Changes Initial V2 release, added new features: - XGATE threads can be interrupted ...
Page 152
... The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used 1. as upper byte) and 0x00 (used as lower byte). The IRQ interrupt can only be handled by the CPU 2. 152 Table 4-2. Terminology Meaning 1 + 0x0010 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 153
... Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 4.3.2.1, “Interrupt Vector Base Register (IVBR)” Freescale Semiconductor for details. for details. S12XS Family Reference Manual, Rev. 1.11 Interrupt (S12XINTV2) for details. ...
Page 154
... Figure 4-1. XINT Block Diagram S12XS Family Reference Manual, Rev. 1.11 Wake Up CPU Vector Address IVBR New IPL Current IPL XGATE Request Route, Priority Level = bits from the channel configuration in the associated configuration register = Interrupt Vector Base = Interrupt Processing Level Freescale Semiconductor ...
Page 155
... Freescale Semiconductor Table 4-3. XINT Memory Map Use RESERVED Interrupt Vector Base Register (IVBR) RESERVED XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Interrupt Request Configuration Address Register (INT_CFADDR) Interrupt Request Configuration Data Register 0 (INT_CFDATA0) Interrupt Request Confi ...
Page 156
... RQST W 0x012C INT_CFDATA4 R RQST W 0x012D INT_CFDATA5 R RQST W 0x012E INT_CFDATA6 R RQST W 0x012F INT_CFDATA7 R RQST W 156 IVB_ADDR[7:0 INT_CFADDR[7: Unimplemented or Reserved Figure 4-2. XINT Register Summary S12XS Family Reference Manual, Rev. 1. Bit 0 0 XILVL[2: PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] 0 PRIOLVL[2:0] Freescale Semiconductor ...
Page 157
... XGATE module. Out of reset the priority is set to the lowest active level (“1”). Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0. Freescale Semiconductor 5 4 ...
Page 158
... Table 4-6. XGATE Interrupt Priority Levels XILVL1 XILVL0 0 0 Interrupt request is disabled Table 4-7. INT_CFADDR Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Meaning Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level Freescale Semiconductor ...
Page 159
... Figure 4-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2) Please refer to the notes following the PRIOLVL[2:0] description below. 1 Address: 0x012B RQST W Reset Unimplemented or Reserved Figure 4-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3) Please refer to the notes following the PRIOLVL[2:0] description below. 1 Freescale Semiconductor ...
Page 160
... Please refer to the notes following the PRIOLVL[2:0] description below. 1 Address: 0x012F RQST W Reset Unimplemented or Reserved Figure 4-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7) Please refer to the notes following the PRIOLVL[2:0] description below. 1 Read: Anytime Write: Anytime 160 S12XS Family Reference Manual, Rev. 1. PRIOLVL[2: PRIOLVL[2: PRIOLVL[2: PRIOLVL[2: Freescale Semiconductor ...
Page 161
... The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. Freescale Semiconductor Description Table 4-9. Interrupt Priority Levels ...
Page 162
... IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction. 162 NOTE S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 163
... If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. Freescale Semiconductor Section 4.3.2.4, “Interrupt Request Section 4.3.2.2, “XGATE Interrupt Priority Configuration Register S12XS Family Reference Manual, Rev ...
Page 164
... Memory Protection Unit (MPU) and an XGATE co-processor 2 only implemented if device features a Memory Protection Unit (MPU) 3 164 NOTE Table 4-10. Generally, all non-maskable interrupts have higher priorities 2 3 S12XS Family Reference Manual, Rev. 1.11 Source Freescale Semiconductor ...
Page 165
... Service interrupt, e.g., clear interrupt flags, copy data, etc. • Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Interrupt (S12XINTV2) Figure 4- 165 ...
Page 166
... Interrupt request channels which are configured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU. 166 RTI L7 L3 (Pending (Pending) Figure 4-14. Interrupt Processing Example S12XS Family Reference Manual, Rev. 1. RTI RTI RTI Freescale Semiconductor 0 ...
Page 167
... SYNC command to determine communication rate • GO_UNTIL command • Hardware handshake protocol to increase the performance of the serial communication Freescale Semiconductor Table 5-1. Revision History Description of Changes - First version of S12XBDMV2 - Introduced standardized Revision History Table S12XS Family Reference Manual, Rev. 1.11 ...
Page 168
... If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or EEPROM) other than allowing erasure. For more information please see 168 S12XS Family Reference Manual, Rev. 1.11 Section 5.4.1, “Security”. Freescale Semiconductor ...
Page 169
... A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. Freescale Semiconductor Figure 5-1. Data ...
Page 170
... CCR6 CCR5 CCR4 = Unimplemented, Reserved = Indeterminate Figure 5-2. BDM Register Summary S12XS Family Reference Manual, Rev. 1.11 Size (Bytes 240 Figure 5-2. Registers are accessed TRACE UNSEC CLKSW CCR3 CCR2 CCR1 = Implemented (do not alter) = Always read zero 0 Freescale Semiconductor Bit CCR0 ...
Page 171
... CLKSW is read debugging environment in emulation modes when the device is not secured and read as 0 when 2 secured if emulation modes available. UNSEC is read debugging environment in special single chip mode when the device is secured and fully erased, 3 else and can only be read if not secure (see also bit description). Freescale Semiconductor ...
Page 172
... TRACE command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands GO_UNTIL. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed 172 Table 5-3. BDMSTS Field Descriptions Description S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 173
... Bus clock dependent on oscillator 1 0 Alternate clock (refer to the device specification to determine the alternate clock source Bus clock dependent on the PLL Freescale Semiconductor Description Table 5-4. BDM Clock Sources BDMCLK S12XS Family Reference Manual, Rev. 1.11 Background Debug Module (S12XBDMV2) 173 ...
Page 174
... The BDM CCR HIGH holding register can be written to modify the CCR value. 174 CCR6 CCR5 CCR4 NOTE S12XS Family Reference Manual, Rev. 1. CCR3 CCR2 CCR1 CCR0 register CCR10 CCR9 CCR8 0 0 Freescale Semiconductor ...
Page 175
... Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see Section 5.4.3, “BDM Hardware “Security”). Firmware commands can only be executed when the system is not secure and is in active background debug mode (BDM). Freescale Semiconductor BGP5 BGP4 ...
Page 176
... BDM. However, these registers are not readable by user programs. BDM is enabled and active immediately out of special single-chip reset. 1. This method is provided by the S12X_DBG module. 2. 176 NOTE S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 177
... WRITE_BD_WORD CC 16-bit address 16-bit data in WRITE_BYTE C0 16-bit address 16-bit data in Freescale Semiconductor Table 5-6. Table 5-6. Hardware Commands Data None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. None Enable Handshake. Issues an ACK pulse after the command is executed. ...
Page 178
... The firmware commands are shown in 178 Table 5-6. Hardware Commands (continued) Data Write to memory with standard BDM firmware lookup table out of map. Must be aligned access. Section 5.4.2, “Enabling and Activating Table 5-7. S12XS Family Reference Manual, Rev. 1.11 Description BDM”. Freescale Semiconductor ...
Page 179
... If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Freescale Semiconductor Table 5-7. Firmware Commands Data Increment X index register 2), then write word to location pointed ...
Page 180
... If the bus rate of the target processor is unknown or could be changing or the external wait function is used recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. 180 Section 5.4.11, “Serial Out”). NOTE NOTE S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 181
... BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See 1. and Section 5.3.2.1, “BDM Status Register (BDMSTS)” Freescale Semiconductor 16 Bits 150-BC AT ~16 TC/Bit Delay Address ...
Page 182
... The host should sample the bit level about 10 target clock cycles after it started the bit time. 182 Figure 5-8 and that of target-to-host in Target Senses Bit 10 Cycles Figure 5-9 shows the host receiving a logic 1 from the target S12XS Family Reference Manual, Rev. 1.11 Figure 5-9 and Earliest Start of Next Bit Freescale Semiconductor ...
Page 183
... BKGD Pin Target System Speedup Pulse High-Impedance Perceived Start of Bit Time BKGD Pin Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1) Freescale Semiconductor High-Impedance R-C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin S12XS Family Reference Manual, Rev. 1.11 Background Debug Module (S12XBDMV2) ...
Page 184
... CPU bus frequency, which in some cases could be very slow 184 High-Impedance 10 Cycles 10 Cycles Host Samples BKGD Pin Figure 5-11). This pulse is referred to as the ACK pulse. S12XS Family Reference Manual, Rev. 1.11 Speedup Pulse Earliest Start of Next Bit Freescale Semiconductor ...
Page 185
... BKGD Pin READ_BYTE Byte Address Host Target Figure 5-12. Handshake Protocol at Command Level Freescale Semiconductor 16 Cycles Speedup Pulse Minimum Delay From the BDM Command NOTE Target BDM Executes the ...
Page 186
... ACK pulse will be aborted. A pending GO, TRACE1 or 186 specifies the timing when the BKGD pin is being driven, so the host NOTE NOTE Pulse”, and assumes that the pending command S12XS Family Reference Manual, Rev. 1.11 Procedure”. Freescale Semiconductor ...
Page 187
... Figure 5-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Freescale Semiconductor NOTE SYNC Response From the Target ...
Page 188
... BDM commands. 188 At Least 128 Cycles ACK Pulse High-Impedance Electrical Conflict Host and Target Drive to BKGD Pin 16 Cycles NOTE and Section 5.4.4, “Standard BDM Firmware Commands” S12XS Family Reference Manual, Rev. 1.11 Speedup Pulse Freescale Semiconductor ...
Page 189
... The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Background Debug Module (S12XBDMV2) ...
Page 190
... TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system 190 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 191
... The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. Freescale Semiconductor S12XS Family Reference Manual, Rev. 1.11 Background Debug Module (S12XBDMV2) ...
Page 192
... Background Debug Module (S12XBDMV2) 192 S12XS Family Reference Manual, Rev. 1.11 Freescale Semiconductor ...
Page 193
... Device User Guide, describing the features of the device into which the DBG is integrated WORD 16 bit data entity Data Line 64 bit data entity Freescale Semiconductor Table 6-1. Revision History Description of Changes - Clarified reserved State Sequencer encodings. - Added single databyte comparison limitation information - Added statement about interrupt vector fetches whilst tagging ...
Page 194
... CPU12X breakpoint executing SWI on breakpoint (SWI) • TRIG Immediate software trigger independent of comparators • Four trace modes — Normal: change of flow (COF) PC information is stored (see flow definition. 194 Table 6-2. Glossary Of Terms (continued) Definition S12XS Family Reference Manual, Rev. 1.11 Section 6.4.5.2.1) for change of Freescale Semiconductor ...
Page 195
... BDM MCU Enable Active Secure Freescale Semiconductor Comparator Breakpoints Matches Enabled Possible Yes Yes Yes Only SWI Active BDM not possible when not enabled Yes Yes No No S12XS Family Reference Manual, Rev. 1.11 S12X Debug (S12XDBGV3) Module Tagging Tracing Possible Possible ...
Page 196
... TRANGE S12XS Family Reference Manual, Rev. 1.11 TAGS BREAKPOINT REQUESTS S12XCPU TRIGGER TAG & STATE LOGIC STATE SEQUENCER STATE TRACE CONTROL TRIGGER TRACE BUFFER Table 6-2. Detailed reserved COMRV DBGBRK 0 SSF2 SSF1 TRCMOD TALIGN CDCM ABCM Freescale Semiconductor Bit 0 SSF0 ...
Page 197
... S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0] Freescale Semiconductor 6 5 ...
Page 198
... ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI 198 reserved BDM DBGBRK NOTE NOTE Table 6-4. DBGC1 Field Descriptions Description S12XS Family Reference Manual, Rev. 1. reserved COMRV Freescale Semiconductor ...
Page 199
... If a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Freescale Semiconductor Description Table 6-5. COMRV Encoding ...
Page 200
... Reserved 5 4 TRANGE 0 0 WARNING preventing proper operation. Table 6-8. DBGTCR Field Descriptions Description Table 6-9. Section 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow 6-11. S12XS Family Reference Manual, Rev. 1.11 State1 State2 State3 TRCMOD TALIGN Freescale Semiconductor 0 0 ...