R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet
R5F21324CNSP#U0
Specifications of R5F21324CNSP#U0
Related parts for R5F21324CNSP#U0
R5F21324CNSP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/32C Group 16 Hardware Manual RENESAS MCU R8C FAMILY / R8C/3x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) Address XXXXh Bit b7 b6 Symbol XXX7 XXX6 After Reset 0 0 Bit Symbol b0 XXX0 XXX bit b1 XXX1 b2 — ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication Interface ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List ............................................................................................................................................... 4 1.3 Block Diagram ......................................................................................................................................... 5 1.4 Pin Assignment .......................................................................................................................................... 6 1.5 Pin ...
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Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 36 5.8 Reset Source Determination Function ..................................................................................................... 36 6. Voltage Detection Circuit .............................................................................................................. 37 6.1 Overview ................................................................................................................................................. 37 6.2 Registers .................................................................................................................................................. 41 6.2.1 Voltage Monitor Circuit Control Register (CMPA) ........................................................................... 41 6.2.2 Voltage ...
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Bus ................................................................................................................................................ 86 9. Clock Generation Circuit ............................................................................................................... 88 9.1 Overview ................................................................................................................................................. 88 9.2 Registers .................................................................................................................................................. 91 9.2.1 System Clock Control Register 0 (CM0) ............................................................................................ 91 9.2.2 System Clock Control Register 1 (CM1) ............................................................................................ 92 9.2.3 System Clock Control ...
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Protect Register (PRCR) ................................................................................................................... 121 11. Interrupts ..................................................................................................................................... 122 11.1 Overview ............................................................................................................................................... 122 11.1.1 Types of Interrupts ............................................................................................................................ 122 11.1.2 Software Interrupts ........................................................................................................................... 123 11.1.3 Special Interrupts .............................................................................................................................. 124 11.1.4 Peripheral Function Interrupts .......................................................................................................... 124 11.1.5 Interrupts and Interrupt ...
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Forced Erase Function ........................................................................................................................... 151 12.4 Standard Serial I/O Mode Disabled Function ....................................................................................... 151 12.5 Notes on ID Code Areas ........................................................................................................................ 152 12.5.1 Setting Example of ID Code Areas ................................................................................................... 152 13. Option Function Select Area ....................................................................................................... 153 13.1 ...
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DTC Activation Source Acknowledgement and Interrupt Source Flags .......................................... 184 15.4 Notes on DTC ........................................................................................................................................ 186 15.4.1 DTC activation source ...................................................................................................................... 186 15.4.2 DTCENi ( Registers .................................................................................................. 186 15.4.3 Peripheral Modules ........................................................................................................................... 186 ...
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Programmable One-shot Generation Mode ........................................................................................... 217 18.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode ............ 218 18.5.2 Operating Example ........................................................................................................................... 219 18.5.3 One-Shot Trigger Selection .............................................................................................................. 220 18.6 Programmable Wait One-Shot Generation Mode ................................................................................. 221 ...
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Timer RC Control Register 1 (TRCCR1) in PWM Mode ................................................................ 260 19.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode ................................................................ 260 19.6.3 Operating Example ........................................................................................................................... 262 19.7 PWM2 Mode ......................................................................................................................................... 264 19.7.1 Timer RC Control Register 1 ...
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UART0 Receive Buffer Register (U0RB) ........................................................................................ 298 21.2.7 UART0 Pin Select Register (U0SR) ................................................................................................. 299 21.3 Clock Synchronous Serial I/O Mode ..................................................................................................... 300 21.3.1 Measure for Dealing with Communication Errors ........................................................................... 304 21.3.2 Polarity Select Function .................................................................................................................... 305 21.3.3 ...
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SDA Input ......................................................................................................................................... 350 22.5.6 ACK and NACK ............................................................................................................................... 350 22.5.7 Initialization of Transmission/Reception .......................................................................................... 350 22.6 Multiprocessor Communication Function ............................................................................................. 351 22.6.1 Multiprocessor Transmission ............................................................................................................ 354 22.6.2 Multiprocessor Reception ................................................................................................................. 355 22.6.3 RXD2 Digital Filter Select Function ................................................................................................ ...
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I/O Function Pin Select Register (PINSR) ....................................................................................... 395 25.2.4 IIC bus Transmit Data Register (ICDRT) ......................................................................................... 396 25.2.5 IIC bus Receive Data Register (ICDRR) .......................................................................................... 396 25.2.6 IIC bus Control Register 1 (ICCR1) ................................................................................................. 397 25.2.7 IIC bus Control ...
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A/D Mode Register (ADMOD) ........................................................................................................ 447 27.2.4 A/D Input Select Register (ADINSEL) ............................................................................................ 448 27.2.5 A/D Control Register 0 (ADCON0) ................................................................................................. 449 27.2.6 A/D Control Register 1 (ADCON1) ................................................................................................. 450 27.3 Common Items for Multiple Modes ...................................................................................................... 451 27.3.1 ...
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Full Status Check .............................................................................................................................. 502 29.5 Standard Serial I/O Mode ...................................................................................................................... 504 29.5.1 ID Code Check Function .................................................................................................................. 504 29.6 Parallel I/O Mode .................................................................................................................................. 507 29.6.1 ROM Code Protect Function ............................................................................................................ 507 29.7 Notes on Flash Memory ........................................................................................................................ 508 ...
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Timer Mode ...................................................................................................................................... 551 32.7.2 Programmable Waveform Generation Mode .................................................................................... 552 32.7.3 Programmable One-shot Generation Mode ...................................................................................... 552 32.7.4 Programmable Wait One-shot Generation Mode ............................................................................. 552 32.8 Notes on Timer RC ................................................................................................................................ 553 32.8.1 TRC Register .................................................................................................................................... 553 32.8.2 ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Module Standby Control Register 0009h System Clock Control ...
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Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch 008Dh ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register ...
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Address Register 0180h Timer RA Pin Select Register 0181h Timer RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register 0189h 018Ah UART2 ...
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Address Register 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer ...
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Address Register 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC ...
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R8C/32C Group RENESAS MCU 1. Overview 1.1 Features The R8C/32C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing ...
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R8C/32C Group 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/32C Group. Table 1.1 Specifications for R8C/32C Group (1) Item Function CPU Central processing unit Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O ...
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R8C/32C Group Table 1.2 Specifications for R8C/32C Group (2) Item Function Serial UART0 Interface UART2 Synchronous Serial Communication Unit (SSU bus LIN Module A/D Converter Comparator B Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature ...
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R8C/32C Group 1.2 Product List Table 1.3 lists Product List for R8C/32C Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/32C Group. Table 1.3 Product List for R8C/32C Group Part No. Program ROM R5F21321CNSP 4 ...
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R8C/32C Group 1.3 Block Diagram Figure 1.2 shows a Block Diagram. I/O ports Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RE (8 bits × 1) ...
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R8C/32C Group 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number. P4_2/VREF P4_7/XOUT(/XCOUT) P4_6/XIN(/XCIN) VCC/AVCC P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2) P3_5/SCL/SSCK(/CLK2/TRCIOD) P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC) Notes: Figure 1.3 Pin Assignment (Top View) REJ09B0573-0100 Rev.1.00 Dec. 18, ...
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R8C/32C Group Table 1.4 Pin Name Information by Pin Number Pin Control Pin Port Number 1 P4_2 2 MODE 3 RESET 4 XOUT(/XCOUT) P4_7 5 VSS/AVSS 6 XIN(/XCIN) P4_6 7 VCC/AVCC 8 P3_7 9 P3_5 10 P3_4 11 P3_3 12 ...
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R8C/32C Group 1.5 Pin Functions Tables 1.5 and 1.6 list Pin Functions. Table 1.5 Pin Functions (1) Item Pin Name Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock input XIN ...
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R8C/32C Group Table 1.6 Pin Functions (2) Item Reference voltage input VREF A/D converter AN8 to AN11 ADTRG Comparator B IVCMP1, IVCMP3 IVREF1, IVREF3 I/O port P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 to P4_7 Input port P4_2 I: ...
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R8C/32C Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 R2 R3 ...
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R8C/32C Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) ...
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R8C/32C Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set ...
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R8C/32C Group 3. Memory 3.1 R8C/32C Group Figure 3 Memory Map of R8C/32C Group. The R8C/32C Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with ...
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R8C/32C Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers and Table 4.13 lists the ID Code Areas and Option Function ...
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R8C/32C Group Table 4.2 SFR Information (2) Address 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h ...
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R8C/32C Group Table 4.3 SFR Information (3) Address 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC ...
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R8C/32C Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D ...
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R8C/32C Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN ...
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R8C/32C Group Table 4.6 SFR Information (6) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh ...
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R8C/32C Group Table 4.7 SFR Information (7) Address 0180h Timer RA Pin Select Register 0181h Timer RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h 0185h 0186h 0187h 0188h UART0 ...
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R8C/32C Group Table 4.8 SFR Information (8) Address 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h ...
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R8C/32C Group Table 4.9 SFR Information (9) Address 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC ...
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R8C/32C Group Table 4.10 SFR Information (10) Address 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h ...
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R8C/32C Group Table 4.11 SFR Information (11) Address 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h ...
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R8C/32C Group Table 4.12 SFR Information (12) Address 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh X: Undefined Note: 1. The ...
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R8C/32C Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit. ...
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R8C/32C Group Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence. Table 5.2 Pin Functions while RESET Pin Level is “L” Pin ...
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R8C/32C Group 5.1 Registers 5.1.1 Processor Mode Register 0 (PM0) Address 0004h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 PM03 Software reset bit b4 — Nothing ...
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R8C/32C Group 5.1.3 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...
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R8C/32C Group 5.1.4 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — After Reset Bit Symbol b0 WDTUFS0 Watchdog timer underflow period set bit b1 WDTUFS1 b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 WDTRCS1 ...
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R8C/32C Group 5.2 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer ...
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R8C/32C Group VCC RESET Figure 5.4 Example of Hardware Reset Circuit and Operation RESET Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation REJ09B0573-0100 Rev.1.00 Dec. 18, 2009 Page 32 of 573 ...
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R8C/32C Group 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, ...
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R8C/32C Group 5.4 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. To use voltage ...
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R8C/32C Group 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning ...
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R8C/32C Group 5.7 Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during ...
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R8C/32C Group 6. Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. 6.1 Overview The detection voltage of voltage detection ...
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R8C/32C Group VCC Level Selection Circuit (4 levels) VDSEL1 to VDSEL0 Level Selection Circuit (16 levels) VD1S3 to VD1S0 Figure 6.1 Voltage Detection Circuit Block Diagram REJ09B0573-0100 Rev.1.00 Dec. 18, 2009 Page 38 of 573 VCA25 + - ≥ Vdet0 ...
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R8C/32C Group Voltage detection 0 circuit Level selection VCC VDSEL1 to VDSEL0 Internal reference voltage VW0C0: Bit in VW0C register VCA25: Bit in VCA2 register VDSEL0, VDSEL1: Bits in OFS register Figure 6.2 Block Diagram of Voltage Monitor 0 Reset ...
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R8C/32C Group Voltage detection 2 circuit fOCO-S VCA27 Level VCA13 VCC change + Voltage - detection 2 signal Internal reference voltage When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. Watchdog timer block Watchdog ...
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R8C/32C Group 6.2 Registers 6.2.1 Voltage Monitor Circuit Control Register (CMPA) Address 0030h Bit b7 b6 Symbol COMPSEL — After Reset 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 — b4 IRQ1SEL Voltage monitor 1 interrupt ...
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R8C/32C Group 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) Address 0031h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. ...
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R8C/32C Group 6.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...
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R8C/32C Group 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) Address 0036h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 VD1S0 Voltage detection 1 level select bit (Reference voltage when the voltage falls) b1 VD1S1 ...
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R8C/32C Group 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Address 0038h Bit b7 b6 Symbol — — After Reset 1 1 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 1 ...
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R8C/32C Group 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Bit b7 b6 Symbol VW1C7 — After Reset 1 0 Bit Symbol b0 VW1C0 Voltage monitor 1 reset interrupt enable (1) bit b1 VW1C1 Voltage monitor 1 digital ...
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R8C/32C Group 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Bit b7 b6 Symbol VW2C7 — After Reset 1 0 Bit Symbol b0 VW2C0 Voltage monitor 2 interrupt enable bit b1 VW2C1 Voltage monitor 2 digital filter disable ...
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R8C/32C Group 6.2.9 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...
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R8C/32C Group 6.3 VCC Input Voltage 6.3.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register ...
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R8C/32C Group 6.4 Voltage Monitor 0 Reset To use voltage monitor 0 reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 reset enabled after reset). Figure 6.5 shows an Operating Example of Voltage Monitor 0 ...
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R8C/32C Group 6.5 Voltage Monitor 1 Interrupt Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of Voltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to ...
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R8C/32C Group Vdet1 (1) 1.8 V VW1C3 bit VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital ...
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R8C/32C Group 6.6 Voltage Monitor 2 Interrupt Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of Voltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to ...
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R8C/32C Group VCC Vdet2 (1) 1.8 V VCA13 bit VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) Voltage monitor 2 interrupt request VW2C1 bit is set to 0 ...
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R8C/32C Group 7. I/O Ports There are 15 I/O ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7 (P4_6 and P4_7 can be used as I/O ports if the XIN clock oscillation circuit and the XCIN clock oscillation circuit ...
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R8C/32C Group 7.2 Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (refer to Table 1.4 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for ...
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R8C/32C Group P1_0 to P1_3 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of A/D converter Note: 1. symbolizes a parasitic diode. Ensure the input voltage ...
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R8C/32C Group P1_4 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function P1_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input ...
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R8C/32C Group P1_6 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Analog input of comparator B P1_7 Direction register Output from individual peripheral function enabled Data bus Port ...
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R8C/32C Group P3_3 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of comparator B Input to external interrupt P3_4 Direction register Output from individual peripheral function ...
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R8C/32C Group P3_5 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function P3_7 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input ...
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R8C/32C Group P4_2/VREF Data bus P4_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Input to external interrupt A/D trigger input Note: 1. symbolizes a parasitic diode. Ensure ...
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R8C/32C Group P4_6/XIN/XCIN Pull-up selection Direction register Data bus Port latch IOINSEL P4_7/XOUT/XCOUT Pull-up selection Direction register Data bus Port latch IOINSEL Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. CM01, ...
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R8C/32C Group MODE MODE signal input RESET RESET signal input Note: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.8 Configuration of I/O Pins REJ09B0573-0100 Rev.1.00 Dec. 18, 2009 Page 64 of 573 symbolizes a ...
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R8C/32C Group 7.4 Registers 7.4.1 Port Pi Direction Register (PDi Address 00E3h (PD1), 00E7h (PD3 Bit b7 b6 Symbol PDi_7 PDi_6 After Reset 0 0 Bit Symbol b0 PDi_0 Port Pi_0 direction bit b1 PDi_1 ...
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R8C/32C Group 7.4.2 Port Pi Register (Pi Address 00E1h(P1), 00E5h(P3 Bit b7 b6 Symbol Pi_7 Pi_6 After Reset X X Bit Symbol b0 Pi_0 Port Pi_0 bit b1 Pi_1 Port Pi_1 bit b2 Pi_2 Port ...
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R8C/32C Group 7.4.3 Timer RA Pin Select Register (TRASR) Address 0180h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRAIOSEL0 TRAIO pin select bit b1 TRAIOSEL1 b2 — Reserved bits b3 — b4 — b5 ...
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R8C/32C Group 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit b1 — Reserved bits b2 — b3 — Nothing is ...
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R8C/32C Group 7.4.7 UART0 Pin Select Register (U0SR) Address 0188h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD0SEL0 TXD0 pin select bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...
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R8C/32C Group 7.4.8 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 TXD2SEL1 b2 — Reserved bit b3 — Nothing is assigned. ...
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R8C/32C Group 7.4.10 SSU/IIC Pin Select Register (SSUIICSR) Address 018Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 IICSEL 2 SSU/I C bus switch bit b1 — Reserved bit b2 — Nothing is assigned. If ...
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R8C/32C Group 7.4.12 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 — Nothing is assigned. If necessary, set ...
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R8C/32C Group 7.4.13 Pull-Up Control Register 0 (PUR0) Address 01E0h Bit b7 b6 Symbol PU07 PU06 After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 PU02 P1_0 to P1_3 pull-up b3 PU03 P1_4 to P1_7 pull-up ...
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R8C/32C Group 7.4.15 Port P1 Drive Capacity Control Register (P1DRR) Address 01F0h Bit b7 b6 Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 After Reset 0 0 Bit Symbol b0 P1DRR0 P1_0 drive capacity b1 P1DRR1 P1_1 drive capacity ...
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R8C/32C Group 7.4.16 Drive Capacity Control Register 0 (DRR0) Address 01F2h Bit b7 b6 Symbol DRR07 DRR06 After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 — Nothing is assigned. If necessary, set to 0. When ...
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R8C/32C Group 7.4.18 Input Threshold Control Register 0 (VLT0) Address 01F5h Bit b7 b6 Symbol VLT07 VLT06 After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 VLT02 P1 input level select bit b3 VLT03 b4 — ...
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R8C/32C Group 7.5 Port Settings Tables 7.5 to 7.25 list the port settings. Table 7.5 Port P1_0/KI0/AN8/TRCIOD Register PD1 KIEN Bit PD1_0 KI0EN Setting Value 0 X ...
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R8C/32C Group Table 7.8 Port P1_3/KI3/AN11/TRCIOC Register PD1 KIEN Bit PD1_3 KI3EN Setting Value ...
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R8C/32C Group Table 7.10 Port P1_5/RXD0/TRAIO/INT1 Register PD1 U0SR Bit PD1_5 RXD0SEL0 0 X Other than 10b 1 X Other than 10b 0 1 Other than 10b Other than 10b Setting 0 X Value X X ...
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R8C/32C Group Table 7.13 Port P3_3/INT3/TRCCLK/SCS/CTS2/RTS2/IVCMP3 Register PD3 SSMR2 INTEN CSS Bit PD3_3 INT3EN Setting X ...
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R8C/32C Group Table 7.15 Port P3_5/SCL/SSCK/TRCIOD/CLK2 Register PD3 SSUIICSR ICCR1 Bit PD3_5 IICSEL ICE Setting 0 Value 1 0 ...
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R8C/32C Group Table 7.17 Port P4_2/VREF Register ADCON1 Bit ADSTBY 0 Setting Value 1 Table 7.18 Port P4_5/INT0/RXD2/SCL2/ADTRG Register PD4 INTEN Bit PD4_5 INT0EN Setting Value ...
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R8C/32C Group Table 7.20 Port P4_7/XOUT/XCOUT Register PD4 CM0 Bit PD4_7 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13 Setting Value ...
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R8C/32C Group Table 7.21 TRBO Pin Setting Register TRBIOC Bit TOCNT TMOD1 0 1 Setting Value 0 0 Table 7.22 TRCIOA Pin Setting Register TRCOER TRCMR Bit EA PWM2 Setting 1 Value ...
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R8C/32C Group 7.6 Unassigned Pin Handling Table 7.26 lists Unassigned Pin Handling. Figure 7.9 shows the Unassigned Pin Handling. Table 7.26 Unassigned Pin Handling Pin Name • After setting to input mode, connect each pin to VSS via a resistor ...
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R8C/32C Group 8. Bus The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/32C Group. ROM, RAM, DTC vector area, DTC control ...
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R8C/32C Group However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH UART2: Registers U2MR, U2BRG, U2TB, U2C0, ...
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R8C/32C Group 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator • Low-speed on-chip oscillator for ...
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R8C/32C Group S Q CM10 = 1 (stop mode) RESET R Power-on reset Software reset Voltage monitor 0 reset Interrupt request S Q WAIT instruction R CM30 Stop signal XOUT/XCOUT XIN/XCIN CM01 = 0 CM13 CM05 CM04 CM01 XIN clock ...
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R8C/32C Group fC fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F fOCO-WDT INT0 Timer f32 CPU clock Figure 9.2 Peripheral Function Clock REJ09B0573-0100 Rev.1.00 Dec. 18, 2009 Page 90 of 573 Watchdog timer A/D converter Timer RB ...
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R8C/32C Group 9.2 Registers 9.2.1 System Clock Control Register 0 (CM0) Address 0006h Bit b7 b6 Symbol CM07 CM06 After Reset 0 0 Bit Symbol Bit Name b0 — Reserved bit b1 CM01 XIN-XCIN switch bit b2 CM02 Wait mode ...
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R8C/32C Group 9.2.2 System Clock Control Register 1 (CM1) Address 0007h Bit b7 b6 Symbol CM17 CM16 After Reset 0 0 Bit Symbol b0 CM10 All clock stop control bit b1 CM11 XIN-XOUT on-chip feedback resistor select bit b2 CM12 ...
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R8C/32C Group 9.2.3 System Clock Control Register 3 (CM3) Address 0009h Bit b7 b6 Symbol CM37 CM36 After Reset 0 0 Bit Symbol b0 CM30 Wait control bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...
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R8C/32C Group CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock, XCIN clock, and the on-chip oscillator clock do not stop, the ...
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R8C/32C Group 9.2.4 Oscillation Stop Detection Register (OCD) Address 000Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 OCD0 Oscillation stop detection enable bit b1 OCD1 Oscillation stop detection interrupt enable bit b2 OCD2 System ...
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R8C/32C Group 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) Address 0023h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA00 High-speed on-chip oscillator enable bit b1 FRA01 High-speed on-chip oscillator select bit b2 — ...
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R8C/32C Group 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) Address 0025h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA20 High-speed on-chip oscillator frequency switching bit b1 FRA21 b2 FRA22 b3 — Reserved bits ...
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R8C/32C Group 9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) Address 0029h Bit b7 b6 Symbol — — After Reset Bit b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the ...
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R8C/32C Group 9.2.14 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...
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R8C/32C Group Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or Step (1) low-speed on-chip oscillator mode Stop XIN clock and Step (2) high-speed on-chip oscillator clock VCA20 ← 1 Step (3) (internal power ...
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R8C/32C Group The clocks generated by the clock generation circuits are described below. 9.3 XIN Clock The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral ...
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R8C/32C Group 9.4 On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register. 9.4.1 Low-Speed On-Chip Oscillator ...
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R8C/32C Group 9.5 XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting ...
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R8C/32C Group 9.6 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit (With XIN and XCIN Pins ...
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R8C/32C Group 9.6.7 fOCO-S fOCO operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on). In wait mode, ...
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R8C/32C Group 9.7 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 9.7.1 Standard Operating Mode Standard operating mode is further separated into four modes. ...
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R8C/32C Group 9.7.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division used as the CPU clock. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 ...
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R8C/32C Group 9.7.2 Wait Mode Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count source protection mode is disabled stop. Since the XIN clock, XCIN clock, and on-chip ...
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R8C/32C Group 9.7.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does ...
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R8C/32C Group Figure 9.6 shows the Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode). To use a peripheral function interrupt to exit wait mode, ...
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R8C/32C Group Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set ...
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R8C/32C Group 9.7.3 Stop Mode Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and the peripheral functions operating with these clocks also stop. The least power required to ...
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R8C/32C Group 9.7.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, ...
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R8C/32C Group Figure 9.9 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed clock mode CM05 = 0 CM07 = 0 CM13 ...
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R8C/32C Group 9.8 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table ...
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R8C/32C Group 9.8.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop ...
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R8C/32C Group Table 9.6 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer Voltage monitor 1 Voltage monitor 2 NO ...
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R8C/32C Group Determination of Interrupt sources NO OCD3 = 1? (XIN clock stops) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock)? Set OCD1 bit to 0 (oscillation stop detection (1) interrupt ...
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R8C/32C Group 9.9 Notes on Clock Generation Circuit 9.9.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 ...
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R8C/32C Group 9.9.3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b. 9.9.4 Oscillation Circuit Constants Consult the oscillator manufacturer ...
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R8C/32C Group 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows: • Registers protected by PRC0 bit: Registers CM0, CM1, ...
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R8C/32C Group 11. Interrupts 11.1 Overview 11.1.1 Types of Interrupts Figure 11.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware Notes: 1. Peripheral function interrupts are generated by the peripheral functions in the MCU not use ...
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R8C/32C Group 11.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 11.1.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when the UND instruction is executed. 11.1.2.2 Overflow Interrupt An overflow ...
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R8C/32C Group 11.1.3 Special Interrupts Special interrupts are non-maskable. 11.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer. 11.1.3.2 Oscillation Stop Detection Interrupt An oscillation stop detection interrupt ...
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R8C/32C Group 11.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in ...
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R8C/32C Group 11.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.2 Relocatable Vector Tables Interrupt Source ( ...
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R8C/32C Group 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC), 0072h ...
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R8C/32C Group 11.2.2 Interrupt Control Register (FMRDYIC, TRCIC, SSUIC/IICIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 004Fh (SSUIC/IICIC Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority level select bit b1 ILVL1 b2 ILVL2 b3 ...
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R8C/32C Group 11.2.3 INTi Interrupt Control Register (INTiIC Address 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority level select bit b1 ...
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R8C/32C Group 11.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 ...
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R8C/32C Group 11.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruction is being executed, the ...
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R8C/32C Group 11.3.5 Interrupt Response Time Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response ...
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R8C/32C Group 11.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the ...
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R8C/32C Group The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 11.6 shows the Register Saving Operation. Stack Address [SP]−5 PCL [SP]−4 [SP]−3 PCM FLGL ...
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R8C/32C Group 11.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved on the stack, are automatically restored. The program, that was running ...
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R8C/32C Group 11.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the Interrupt Priority Level Selection Circuit. Priority level of interrupts Voltage monitor 1 UART2 bus ...
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R8C/32C Group 11.4 INT Interrupt 11.4.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register (enabled). The ...
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R8C/32C Group 11.4.3 External Input Enable Register 0 (INTEN) Address 01FAh Bit b7 b6 Symbol INT3PL INT3EN After Reset 0 0 Bit Symbol b0 INT0EN INT0 input enable bit b1 INT0PL INT0 input polarity select bit b2 INT1EN INT1 input ...
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R8C/32C Group 11.4.5 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in the INTF register. The INTi level is sampled every sampling clock ...
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R8C/32C Group 11.5 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or ...
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R8C/32C Group 11.5.1 Key Input Enable Register 0 (KIEN) Address 01FEh Bit b7 b6 Symbol KI3PL KI3EN After Reset 0 0 Bit Symbol b0 KI0EN KI0 input enable bit b1 KI0PL KI0 input polarity select bit b2 KI1EN KI1 input ...
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R8C/32C Group 11.6 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a break function ...
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R8C/32C Group 11.6.1 Address Match Interrupt Enable Register i (AIERi Address 01C3h (AIER0), 01C7h (AIER1) Bit b7 b6 Symbol — — After Reset 0 0 Symbol — — After Reset 0 0 Bit Symbol b0 ...
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R8C/32C Group 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) The timer RC interrupt, synchronous serial communication unit interrupt, I memory interrupt each have multiple ...
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R8C/32C Group As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I bus interface interrupt, and flash memory interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and ...
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R8C/32C Group 11.8 Notes on Interrupts 11.8.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the ...
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R8C/32C Group 11.8.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after ...
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R8C/32C Group 11.8.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated interrupt request may be generated, disable the interrupt before ...
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R8C/32C Group 12. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from being read, rewritten, or ...
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R8C/32C Group 12.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and ...
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R8C/32C Group 12.3 Forced Erase Function This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the on- chip debugging emulator are “ALeRASE” in ASCII code, the content of the user ...
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R8C/32C Group 12.5 Notes on ID Code Areas 12.5.1 Setting Example of ID Code Areas The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. The following ...
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R8C/32C Group 13. Option Function Select Area 13.1 Overview The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. The reset ...
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R8C/32C Group 13.2 Registers Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. 13.2.1 Option Function Select Register (OFS) Address 0FFFFh ...
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R8C/32C Group 13.2.2 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — After Reset Bit Symbol b0 WDTUFS0 Watchdog timer underflow period set bit b1 WDTUFS1 b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 WDTRCS1 ...
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R8C/32C Group 13.3 Notes on Option Function Select Area 13.3.1 Setting Example of Option Function Select Area The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a ...
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R8C/32C Group 14. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. 14.1 Overview The watchdog timer contains ...
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R8C/32C Group Prescaler 1/16 1/128 CPU clock 1/2 Low-speed on-chip oscillator for watchdog timer Oscillation starts when CSPRO = 1 Internal reset signal (“L” active) Bits WDTRCS0 and WDTRCS1 Write to WDTR register Note value set by bits ...
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R8C/32C Group 14.2 Registers 14.2.1 Processor Mode Register 1 (PM1) Address 0005h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 PM12 WDT interrupt/reset switch bit b3 — Nothing is ...
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R8C/32C Group 14.2.4 Watchdog Timer Control Register (WDTC) Address 000Fh Bit b7 b6 Symbol WDTC7 — After Reset 0 0 Bit Symbol b0 — The following bits of the watchdog timer can be read. When bits WDTUFS1 to WDTUFS0 in ...
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R8C/32C Group 14.2.6 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...
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R8C/32C Group 14.2.7 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — After Reset Bit Symbol b0 WDTUFS0 Watchdog timer underflow period set bit b1 WDTUFS1 b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 WDTRCS1 ...
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R8C/32C Group 14.3 Functional Description 14.3.1 Common Items for Multiple Modes 14.3.1.1 Refresh Acknowledgment Period The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can be selected by bits WDTRCS0 and WDTRCS1 in the ...
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R8C/32C Group 14.3.2 Count Source Protection Mode Disabled The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled). Table 14.2 ...
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R8C/32C Group 14.3.3 Count Source Protection Mode Enabled The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when count source protection mode is enabled. If the CPU clock stops when a program ...
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R8C/32C Group 15. DTC The DTC (data transfer controller function that transfers data between the SFR and on-chip memory without using the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt ...
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R8C/32C Group DTCENi ( DTCTL Peripheral interrupt request Interrupt controller Figure 15.1 DTC Block Diagram 15.2 Registers When the DTC is activated, control data (DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj ...
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R8C/32C Group 15.2.1 DTC Control Register j (DTCCRj 23) Address Refer to Table 15.4 Control Data Allocation Addresses. Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 MODE Transfer mode select bit ...
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R8C/32C Group 15.2.3 DTC Transfer Count Register j (DTCCTj 23) Address Refer to Table 15.4 Control Data Allocation Addresses. Bit b7 b6 Symbol — — After Reset X X Bit These bits specify ...
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R8C/32C Group 15.2.7 DTC Activation Enable Register i (DTCENi Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Dh (DTCEN5), 008Eh (DTCEN6) Bit b7 b6 Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 After Reset ...
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R8C/32C Group 15.2.8 DTC Activation Control Register (DTCTL) Address 0080h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bit b1 NMIF Non-maskable interrupt generation (1) bit b2 — Nothing is assigned. If necessary, ...