R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 110

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 81 of 573
Table 7.15
X: 0 or 1
Notes:
Table 7.16
X: 0 or 1
Notes:
Register
Register
Setting
Setting
Value
Value
Bit
Bit
1.
2.
3.
4.
1.
2.
3.
4.
Pulled up by setting the PU07 bit in the PUR0 register to 1.
Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 (N-channel open-drain output).
N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1.
Pulled up by setting the PU07 bit in the PUR0 register to 1.
Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output).
N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
PD3_7
PD3_5
PD3
PD3
X
X
X
X
X
0
1
0
0
0
0
1
X
X
X
0
X
0
X
SSUIICSR ICCR1
SSUIICSR ICCR1
IICSEL
Port P3_5/SCL/SSCK/TRCIOD/CLK2
Port P3_7/SSO/TXD2/SDA2/RXD2/SCL2/TRAO/SDA
IICSEL
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
ICE
ICE
X
X
X
X
X
X
X
X
X
0
0
1
0
0
0
0
0
X
0
X
0
1
X
X
X
0
X
0
X
0
X
0
Communication Unit (Refer
to Table 24.4 Association
between Communication
SSCK output
SSO output
Communication Unit (Refer
to Table 24.4 Association
between Communication
Modes and I/O Pins .)
control
Modes and I/O Pins .)
control
Synchronous Serial
Synchronous Serial
X
0
X
0
X
0
1
X
0
X
0
X
0
X
0
X
0
X
X
X
X
X
X
X
0
0
0
1
0
0
0
0
SSO input
SSCK input
control
control
X
X
X
X
X
X
X
X
0
0
1
0
0
0
0
0
0
0
X
0
X
X
1
0
0
X
0
X
0
X
0
X
Other than
Other than
Other than
RXD2SEL TXD2SEL
TRCIODSEL
X
X
X
X
X
1
1
1
Other than
Other than
TRCPSR1
1
X
X
X
1
1
X
X
10b
10b
10b
10b
10b
U2SR0
0
X
X
X
0
0
X
X
0
X
X
X
0
0
X
X
Other than
Other than
Other than
Other than
Other than
1
X
X
X
0
0
CLK2SEL0
01b
01b
01b
01b
01b
U2SR1
0
X
X
X
1
1
X
X
X
0
0
0
0
1
1
X
X
2
X
X
X
X
0
0
1
0
X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
2 1 0
0 0 1
SMD
U2MR
SMD
X
X
X
X
X
X
X
1
1
0
1
1
U2MR
CKDIR
0
X
X
X
X
X
X
0
1
0
1
0
0
X
X
X
X
X
X
X
X
1
0
U2SMR TRAIOC
IICM
X
X
X
X
X
X
X
X
Refer to Table
Refer to Table
1
1
7.25 TRCIOD
7.25 TRCIOD
Pin Setting
Pin Setting
Timer RC
Setting
—
X
X
X
X
X
X
X
TOENA
X
X
X
X
X
X
0
0
0
1
Input port
Output port
SCL input/output
SSCK input
SSCK output
TRCIOD input
TRCIOD output
CLK2 input
CLK2 output
Input port
Output port
SDA input/output
SSO input
SSO output
RXD2 input
SCL2 input/
output
TXD2
output
SDA2 input/
output
TRAO output
Function
Function
(2, 4)
(2, 4)
(2, 4)
7. I/O Ports
(1)
(1)
(1)
(2)
(2)
(2)
(1)
(1)
(2, 3)
(2, 4)
(2, 3)
(2)
(1)
(2)
(2)
(2)