R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 139

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 110 of 573
Figure 9.6
Figure 9.6 shows the Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in
CM3 Register is Set to 1 (MCU Enters Wait Mode).
To use a peripheral function interrupt to exit wait mode, set up the following before setting the CM30 bit to 1.
(1) Set the I flag to 0 (maskable interrupt disabled).
(2) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
(3) Operate the peripheral function to be used for exiting wait mode.
When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the VCA20 bit in the VCA2 register, as shown in Figure 9.6.
The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU
exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits
CM16 and CM17 in the CM1 register automatically change.
FMR0 Register
(flash memory
(flash memory
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
FMSTP Bit
operates)
stops)
0
1
Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in
CM3 Register is Set to 1 (MCU Enters Wait Mode)
low consumption disabled)
low consumption enabled)
low consumption enabled)
low consumption disabled
VCA2 Register
(internal power
(internal power
(internal power
(internal power
VCA20 Bit
Wait mode
0
1
0
1
Interrupt request generation
stabilization time
Stabilization Time
Internal power
100 µs (max.)
Internal Power
100 µs (max.)
100 µs (max.)
T0
0 µs
0 µs
(T0)
Period of system clock
Period of system clock
activation sequence
× 1 cycle + 60 µs
Activation (T1)
Flash memory
Flash Memory
Time until
× 1 cycle
(max.)
T1
Period of CPU clock
restart sequence
Same as above
Supply (T2)
CPU Clock
× 2 cycles
Time until
CPU clock
T2
9. Clock Generation Circuit
The total of T0 to
T2 is the time
from wait mode to
first instruction
execution
following exit.
Remarks