R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 150

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 121 of 573
10. Protection
The protection function protects important registers from being easily overwritten if a program runs out of control.
The registers protected by the PRCR register are as follows:
• Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C
10.1
10.1.1
Notes:
After Reset
1. The PRC2 bit is set to 0 after setting it to 1 (write enabled) and writing to the SFR area. Change the register
2. Bits PRC0, PRC1, and PRC3 are not set to 0 even after setting them to 1 (write enabled) and writing to the SFR
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000Ah
protected by the PRC2 bit with the next instruction after that used to set the PRC2 bit to 1. Do not allow interrupts
or DTC activation between the instruction to set to the PRC2 bit to 1 and the next instruction.
areas. Set these bits to 0 by a program.
Symbol
Register
Symbol
PRC0
PRC1
PRC3
Bit
Protect Register (PRCR)
—
—
—
—
—
b7
—
0
Protect bit 0
Protect bit 1
Reserved bit
Protect bit 3
Reserved bits
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Bit Name
b6
—
0
b5
—
0
Enables writing to registers CM0, CM1, CM3, OCD, FRA0,
FRA1, FRA2, and FRA3.
0: Write disabled
1: Write enabled
Enables writing to registers PM0 and PM1.
0: Write disabled
1: Write enabled
Enables writing to registers OCVREFCR, VCA2, VD1LS,
VW0C, VW1C, and VW2C.
0: Write disabled
1: Write enabled
Set to 0.
Set to 0.
b4
—
0
PRC3
b3
0
(2)
(2)
(2)
b2
—
0
Function
PRC1
b1
0
PRC0
b0
0
10. Protection
R/W
R/W
R/W
R/W
R/W
R/W
—