R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 159

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 130 of 573
Table 11.3
11.3
Bits ILVL2 to ILVL0
000b
001b
010b
011b
100b
101b
110b
111b
11.3.1
11.3.2
11.3.3
The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority.
This description does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register
to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in
the corresponding interrupt control register.
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. After the interrupt request is
acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt
requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC interrupt, the synchronous serial communication unit interrupt,
the I
Synchronous Serial Communication Unit Interrupt, I
Interrupt (Interrupts with Multiple Interrupt Request Sources).
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are the conditions when an interrupt is acknowledged:
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
I flag = 1
IR bit = 1
Interrupt priority level > IPL
Interrupt Control
2
C bus interface interrupt, and the flash memory interrupt are different. Refer to 11.7 Timer RC Interrupt,
I Flag
IR Bit
Bits ILVL2 to ILVL0, IPL
Settings of Interrupt Priority
Levels
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority Level
Priority
High
Low
Table 11.4
000b
001b
010b
011b
100b
101b
110b
111b
2
IPL
C bus Interface Interrupt, and Flash Memory
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Enabled Interrupt Priority Level
11. Interrupts

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